公开(公告)号：JPH11274496A

公开(公告)日：1999-10-08

申请号：JP3112599

申请日：1999-02-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66537

Abstract: PROBLEM TO BE SOLVED: To form a threshold adjusting implant located only under a channel, by implanting a threshold adjusting dopant through a gate hole or a punch- through adjusting dopant after defining the gate hole on a dielectric stack.
SOLUTION: After defining a gate hole 40 in a dielectric stack, either a threshold adjusting dopant or a punch-through dopant is implanted through the hole 40. Since the hole 40 allows the dopant to reach only a region just under the hole 40, the implantation of the dopant is effected by an accurately controlled method. The dimensions and shape of the hole 40 determine the dimensions and shape of the threshold adjusting implant. Therefore, the threshold adjusting implant located only under a channel can be formed.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了形成仅位于通道下方的阈值调节植入物，通过在限定电介质叠层上的栅极孔之后通过栅极孔或穿通调节掺杂剂注入阈值调节掺杂剂。 解决方案：在电介质叠层中定义栅极孔40之后，通过孔40注入阈值调节掺杂剂或穿通掺杂剂。由于孔40允许掺杂剂仅到达孔40正下方的区域，因此， 通过精确控制的方法实现掺杂剂的注入。 孔40的尺寸和形状决定了阈值调节植入物的尺寸和形状。 因此，可以形成仅位于通道下方的阈值调节植入物。

公开(公告)号：JP2006135319A

公开(公告)日：2006-05-25

申请号：JP2005309279

申请日：2005-10-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  CAI JUAN ,  KEVIN K CHAN ,  MOONEY PATRICIA M ,  KERN LIM

IPC: H01L21/20 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure for use in n-type and p-type MOSFET devices, and the method of manufacturing the same.
SOLUTION: A semiconductor structure is formed such that the layer structure of a wafer region by which an n-type MOSFET is manufactured is different from the layer structure of a wafer region by which a p-type MOSFET is manufactured. First, the structure is manufactured by forming a damage region on the front surface of an Si content substrate by ion implantation of a light atom such as He. Then, strained SiGe alloy is formed on the Si content substrate comprising the damage region. Then, the strained SiGe alloy is made to ease substantially by strained relaxation resulting from defect using an anneal step. Then, a strained semiconductor cap of strained Si etc. is formed on the strained SiGe alloy.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供用于n型和p型MOSFET器件的半导体结构及其制造方法。 解决方案：形成半导体结构，使得制造n型MOSFET的晶片区域的层结构不同于制造p型MOSFET的晶片区域的层结构。 首先，通过用诸如He的光原子的离子注入在Si含量衬底的前表面上形成损伤区域来制造结构。 然后，在包含损伤区域的Si含量基板上形成应变SiGe合金。 然后，使应变SiGe合金基本上通过使用退火步骤的缺陷导致的应变弛豫来简化。 然后，在应变SiGe合金上形成应变Si等的应变半导体盖。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005019996A

公开(公告)日：2005-01-20

申请号：JP2004183756

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DAINE C BOYD ,  IEONG MEIKEI ,  KANARSKY THOMAS S ,  KEDZIERSKI JAKUB T ,  YANG MIN

IPC: H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor circuit including at least one FinFET device and at least one planer single-gate FET device on a same SOI semiconductor substrate.
SOLUTION: The integrated semiconductor circuit includes a FinFET and a planer single-gate FET located on an embedded insulating layer of a silicon-on-insulator (SOI) substrate. The planer single FET is located on a surface of a patterned top semiconductor layer of the SOI substrate; and the FinFET has a vertical channel perpendicular to the planer single-gate FET. In a method for forming such an integrated circuit, when width of the FinFET active device region is trimmed, a formed resist image and a patterned hard mask are used, and after that the formed resist image and etching are used when thickness of the FET device region is reduced. The trimmed active FinFET device region is formed such that it is perpendicular to the planer single-gate FET device region whose thickness has been reduced.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供在同一SOI半导体衬底上包括至少一个FinFET器件和至少一个平面单栅极FET器件的集成半导体电路。 解决方案：集成半导体电路包括位于绝缘体上硅（SOI）衬底的嵌入式绝缘层上的FinFET和平面单栅极FET。 平面单个FET位于SOI衬底的图案化顶部半导体层的表面上; 并且FinFET具有垂直于平面单栅极FET的垂直沟道。 在形成这种集成电路的方法中，当FinFET有源器件区域的宽度被修整时，使用形成的抗蚀剂图像和图案化的硬掩模，然后在FET器件的厚度时使用所形成的抗蚀剂图像和蚀刻 区域减少。 经修整的有源FinFET器件区域形成为使其垂直于厚度已经减小的平面单栅极FET器件区域。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000340552A

公开(公告)日：2000-12-08

申请号：JP2000124026

申请日：2000-04-25

Applicant: IBM

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  WOLDEMAR W KOKON ,  WILLIAM C WILEY ,  RICHARD WISE

IPC: H01L29/417 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To pattern a silicon nitride layer so that it has a high aspect ratio by etching an exposed part of the silicon nitride layer with a high density plasma generated by exciting an etchant gas which includes a polymerizing agent, a source of hydrogen, an oxidant, and a noble gas diluent, to form a trench. SOLUTION: An etchant gas includes a polymerizing agent, a source of hydrogen, an oxidant, and a noble gas diluent. The polymerizing agent is a precursor for causing formation of passivation layer and is preferably selected from among CF4, C2F6, and C3F8. The source of hydrogen is preferably selected from among CHF3, CH2F2, CH3F, and H2, and the oxidant is selected among CO, CO2, and O2. This etchant gas is excited to generate a high density plasma. A part of a silicon nitride layer 131 is exposed by an etch window 133 to etch the exposed part of the silicon nitride layer 131 with the plasma, to form a trench which extends to a silicon oxide layer.

公开(公告)号：JP2006049897A

公开(公告)日：2006-02-16

申请号：JP2005219835

申请日：2005-07-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAINE C BOYD ,  HOLT JUDSON R ,  LEONG MEIKEI ,  MO RENEE T ,  REN ZHIBIN ,  SHAHIDI GHAVAM G

IPC: H01L29/786 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/76283 ,  H01L21/823892 ,  H01L21/84 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a super-steep retrograde well field effect transistor device, and to provide an ultra-thin body FET device manufactured by the same.
SOLUTION: The method for manufacturing a super-steep retrograde well field effect transistor device starts with an SOI layer formed on a substrate, for example, an embedded oxide layer. The SOI layer is thinned so as to form an ultra-thin SOI layer. A separation trench is formed for dividing the SOI layer into an N ground layer region and a P ground layer region. The N and P ground layer regions formed in the SOI layer are doped with N-type and P-type dopants to a high concentration level. A semiconductor channel region is formed on the N and P ground layer regions. The source region and the drain region of the FET and the gate electrode stack on the channel region are formed. As desired, a diffusion retarding layer is formed between the SOI ground layer regions and the channel regions.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于制造超陡逆向井场效应晶体管器件的方法，并提供由其制造的超薄体FET器件。 解决方案：用于制造超陡逆向井场效应晶体管器件的方法从形成在衬底上的SOI层，例如嵌入的氧化物层开始。 SOI层被薄化以形成超薄SOI层。 形成分离沟槽，用于将SOI层分成N个接地层区域和P个接地层区域。 形成在SOI层中的N和P接地层区域以高浓度水平掺杂有N型和P型掺杂剂。 在N和P接地层区域上形成半导体沟道区。 形成FET的源极区域和漏极区域以及沟道区域上的栅电极堆叠。 根据需要，在SOI接地层区域和沟道区域之间形成扩散延迟层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2003332462A

公开(公告)日：2003-11-21

申请号：JP2003109064

申请日：2003-04-14

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： MOCUTA ANDA C ,  IEONG MEIKEI ,  AMOS RICKY S ,  DAINE C BOYD ,  MOCUTA DAN M ,  CHEN HUAJIE

IPC: H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823807 ,  H01L21/823828

Abstract: PROBLEM TO BE SOLVED: To provide a high performance (surface channel) CMOS device provided with a mid gap work function metal gate.
SOLUTION: An epitaxial layer is used for adjustment/reduction of a threshold voltage V
t of PFET region and large amount of reduction in V
t (up to 500 mV) which are required by a CMOS device provided with a mid gap metal gate. In this case, the counter doping using an in-site B (boron) doped epitaxial layer or B and C (carbon) codoped epitaxial layer is provided. Here, the doping of C is important to give a surface channel CMOS device provided with the mid gap metal gate while an excellent short channel effect is maintained by holding the shallow B profile through the additional degree of freedom to relaxing the diffusion of B (even in the case of the subsequent activation heat cycle).
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种具有中间间隙功能金属栅极的高性能（表面通道）CMOS器件。 解决方案：使用外延层来调整/降低PFET区域的阈值电压V t ，并且V T 的大量还原（高达500mV ），这是由设置有中间间隙金属栅极的CMOS器件所需要的。 在这种情况下，提供使用现场B（硼）掺杂外延层或B和C（碳）共掺杂外延层的反掺杂。 这里，C的掺杂对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是重要的，同时通过保持浅的B分布通过附加的自由度来放宽B的扩散（甚至 在随后的活化热循环的情况下）。 版权所有（C）2004，JPO