公开(公告)号：JPH10107013A

公开(公告)日：1998-04-24

申请号：JP20491697

申请日：1997-07-30

Applicant: IBM ,  TOSHIBA CORP ,  SIEMENS AG

Inventor： NAEEM MUNIR D ,  BURNS STUART M ,  CHRISTIE ROSEMARY ,  GREWAL VIRINDER ,  WALTER W KOKON ,  NARITA MASAKI ,  BRUNO SPULER ,  SHII HOA YAN

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

Abstract: PROBLEM TO BE SOLVED: To make more vertical sidewall shape while reducing the corrosion by a method wherein aluminum and aluminum alloy are anisotropically etched away by RIE using specific low power and pressure. SOLUTION: In the title process, aluminum and aluminum alloy are anisotropically etched away by RIE using low power (not exceeding 350W) and low pressure (not exceeding 15mT). Within an upper layer 14 and a bottom layer 10, the physical etching process called sputtering is performed while in a bulk aluminum layer 12, the chemical process is performed. As for the reaction gas of RIE, chlorine, HCl and inert gas (e.g. nitrogen, argon, helium, etc.) are enumerated. Through these procedures, the corrosion of sidewall and the other problems posed by high power RIE can be solved. Besides, a photoresist 16 can be removed more easily while it is released.

公开(公告)号：JP2000340552A

公开(公告)日：2000-12-08

申请号：JP2000124026

申请日：2000-04-25

Applicant: IBM

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  WOLDEMAR W KOKON ,  WILLIAM C WILEY ,  RICHARD WISE

IPC: H01L29/417 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To pattern a silicon nitride layer so that it has a high aspect ratio by etching an exposed part of the silicon nitride layer with a high density plasma generated by exciting an etchant gas which includes a polymerizing agent, a source of hydrogen, an oxidant, and a noble gas diluent, to form a trench. SOLUTION: An etchant gas includes a polymerizing agent, a source of hydrogen, an oxidant, and a noble gas diluent. The polymerizing agent is a precursor for causing formation of passivation layer and is preferably selected from among CF4, C2F6, and C3F8. The source of hydrogen is preferably selected from among CHF3, CH2F2, CH3F, and H2, and the oxidant is selected among CO, CO2, and O2. This etchant gas is excited to generate a high density plasma. A part of a silicon nitride layer 131 is exposed by an etch window 133 to etch the exposed part of the silicon nitride layer 131 with the plasma, to form a trench which extends to a silicon oxide layer.

公开(公告)号：JPH11317524A

公开(公告)日：1999-11-16

申请号：JP3111199

申请日：1999-02-09

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To enable a field effect transistor to be accurately specified in channel length, lessened in source and drain resistance, and minimized in overlap capacitance, by a method wherein a gate hole is demarcated on a dielectric stack, an attached side wall layer is removed from a horizontal plane, and the gate hole is filled up with a gate conductor. SOLUTION: An etching window which is nearly equal in lateral dimension to a gate pillar that is specified in dimensions by a resist mask is provided to a dielectric stack which comprises nitride layers 31 and 38. An RIE process for forming a gate hole is used for transferring the etching window to the dielectric stack. Then, the gate hole is demarcated-by an RIE method, a side wall layer is attached and then removed from a horizontal plane. By this setup, the gate hole is lessened in length by a residual side wall spacer 61. Then, polysilicon is deposited inside the gate hole and on a dielectric stack uppermost layer 38, and the dielectric stack uppermost layer 38 is exposed by flattening the deposited polysilicon.

公开(公告)号：JPH11274496A

公开(公告)日：1999-10-08

申请号：JP3112599

申请日：1999-02-09

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： DAINE C BOYD ,  BURNS STUART M ,  HUSSEIN I HANAPHY ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78

CPC classification number: H01L29/66583 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/66537

Abstract: PROBLEM TO BE SOLVED: To form a threshold adjusting implant located only under a channel, by implanting a threshold adjusting dopant through a gate hole or a punch- through adjusting dopant after defining the gate hole on a dielectric stack.
SOLUTION: After defining a gate hole 40 in a dielectric stack, either a threshold adjusting dopant or a punch-through dopant is implanted through the hole 40. Since the hole 40 allows the dopant to reach only a region just under the hole 40, the implantation of the dopant is effected by an accurately controlled method. The dimensions and shape of the hole 40 determine the dimensions and shape of the threshold adjusting implant. Therefore, the threshold adjusting implant located only under a channel can be formed.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：为了形成仅位于通道下方的阈值调节植入物，通过在限定电介质叠层上的栅极孔之后通过栅极孔或穿通调节掺杂剂注入阈值调节掺杂剂。 解决方案：在电介质叠层中定义栅极孔40之后，通过孔40注入阈值调节掺杂剂或穿通掺杂剂。由于孔40允许掺杂剂仅到达孔40正下方的区域，因此， 通过精确控制的方法实现掺杂剂的注入。 孔40的尺寸和形状决定了阈值调节植入物的尺寸和形状。 因此，可以形成仅位于通道下方的阈值调节植入物。

公开(公告)号：JPH1171689A

公开(公告)日：1999-03-16

申请号：JP17112498

申请日：1998-06-18

Applicant: SIEMENS AG ,  TOSHIBA CORP ,  IBM

Inventor： NAEEM MUNIR D ,  BURNS STUART M ,  GRECO NANCY ,  GRECO STEVE ,  GREWAL VIRINDER ,  LEVINE ERNEST ,  NARITA MASAKI ,  SPULER BRUNO

IPC: C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213

Abstract: PROBLEM TO BE SOLVED: To easily remove the polymer deposition generated during etching by applying high sputtering component etching to at least a part of a first barrier layer and further low sputtering component etching to at least a part of a metallic treatment layer, respectively. SOLUTION: The high sputtering component etching advantageously increases the sputtering of a photoresist layer, allows additive carbon to exist in an etching reactor and this carbon to be absorbed in the side wall deposition. This deposition is made more soluble by increasing the carbon quantity of the side wall deposition and may be made easily removable during the subsequent photoresist stripping and washing stage. The metal treatment layer is usually substantially thicker than the apex barrier layer of most of the laminates and, therefore, the use of the low sputtering component etching to etch the metal treatment layer in order to lessen photoresist corrosion is recommended.

公开(公告)号：SG71909A1

公开(公告)日：2000-04-18

申请号：SG1999000606

申请日：1999-02-15

Applicant: IBM

Inventor： BOYD DIANE C ,  BURNS STUART M ,  HANAFI HUSSEIN I ,  TAUR YUAN ,  WILLE WILLIAM C

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/78

Abstract: A method for the formation of field effect transistors (FETs), and more particularly metal oxide field effect transistors (MOSFETs), comprising the steps of: forming a dielectric stack on a semiconductor structure; defining an etch window on the dielectric stack; defining a gate hole in the dielectric stack by transferring the etch window into the dielectric stack using a reactive ion etching (RIE) process; depositing a side wall layer; removing the side wall layer from horizontal surfaces of the dielectric stack and gate hole such that side wall spacers remain which reduce the lateral size of the gate hole; depositing a gate conductor such that it fills the gate hole; removing the gate conductor covering the portions of the semiconductor structure surrounding the gate hole; removing at least part of the dielectric stack; and removing the side wall spacers.