公开(公告)号：ES2143975T3

公开(公告)日：2000-06-01

申请号：ES91106051

申请日：1991-04-16

Applicant: IBM

Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

公开(公告)号：AT191295T

公开(公告)日：2000-04-15

申请号：AT91106051

申请日：1991-04-16

Applicant: IBM

Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.