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    3.
    发明专利
    未知

    公开(公告)号：AT191295T

    公开(公告)日：2000-04-15

    申请号：AT91106051

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    FAULT TOLERANT MEMORY ERROR CORRECTION: EACH MEMORY UNIT HAS LOCK-UP FEATURE
    4.
    发明专利
    FAULT TOLERANT MEMORY ERROR CORRECTION: EACH MEMORY UNIT HAS LOCK-UP FEATURE 未知

    公开(公告)号：NZ232458A

    公开(公告)日：1992-03-26

    申请号：NZ23245890

    申请日：1990-02-09

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    METHOD AND MEANS OF SHORTENING MEMORY FETCH TIME
    6.
    发明专利
    METHOD AND MEANS OF SHORTENING MEMORY FETCH TIME 未知

    公开(公告)号：CA2044121A1

    公开(公告)日：1992-01-19

    申请号：CA2044121

    申请日：1991-06-07

    Applicant: IBM

    Inventor： CHAN SHIU K ,  DATRES JOSEPH H JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    7.
    发明专利
    未知

    公开(公告)号：DE69132077T2

    公开(公告)日：2000-10-05

    申请号：DE69132077

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    8.
    发明专利
    未知

    公开(公告)号：DE69132077D1

    公开(公告)日：2000-05-04

    申请号：DE69132077

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

    9.
    发明专利
    未知

    公开(公告)号：DE69026743D1

    公开(公告)日：1996-06-05

    申请号：DE69026743

    申请日：1990-02-02

    Applicant: IBM

    Inventor： BLAKE ROBERT MARTIN ,  BOSSEN DOUGLAS CRAIG ,  CHEN CHIN-LONG ,  FIFIELD JOHN ATKINSON ,  KALTER HOWARD LEO ,  LO TIN-CHEE

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/00

    Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

    10.
    发明专利
    未知

    公开(公告)号：ES2143975T3

    公开(公告)日：2000-06-01

    申请号：ES91106051

    申请日：1991-04-16

    Applicant: IBM

    Inventor： CHAN SHIU KWONG ,  DATRES JOSEPH HENRY JR ,  LO TIN-CHEE

    IPC: G06F12/06 ,  G06F12/08 ,  G11C7/22 ,  G11C11/401 ,  G11C11/4076 ,  G11C29/00 ,  G11C29/42 ,  G11C7/00

    Abstract: Speeds up computer memory system operations by providing a memory fetch cycle that is shorter than the memory store cycle. To do this, the invention changes the timing of the recovery part of the fetch operation in the semiconductor memory chips of the memory. Each chip has at least one dynamic random access memory array (DRAM) and a small high speed cache memory (SRAM) on the chip. The system memory controller recognizes the fetch or store state of a memory request in generating a DRAM subrow-address timing signal (RAS) and a cache address timing signal (CAS) for enabling the accessing and addressing of bits in the SRAM and the recovery in the DRAM. The invention controls RAS to start DRAM recovery for a fetch cycle near the start of fetching of data from the SRAMs on the chips, but controls RAS to not start DRAM recovery for a store cycle until SRAM data storing is done. The clocks on the chips contain circuits that enable fetching of data from the SRAMs during DRAM recovery, but that prevent DRAM recovery from starting until data storing in the SRAMs is complete.

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