公开(公告)号：GB2574956B

公开(公告)日：2020-05-20

申请号：GB201913452

申请日：2018-02-20

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  CHUNG-LUNG SHUM ,  COREY STAPPENBECK ,  DAVID ANDREW SCHROTER

IPC: G06F9/30

公开(公告)号：GB2574956A

公开(公告)日：2019-12-25

申请号：GB201913452

申请日：2018-02-20

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  CHUNG-LUNG SHUM ,  COREY STAPPENBECK ,  DAVID ANDREW SCHROTER

IPC: G06F9/30

Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.