公开(公告)号：GB2632957A

公开(公告)日：2025-02-26

申请号：GB202416053

申请日：2023-01-17

Applicant: IBM

Inventor： ADAM COLLURA ,  MICHAEL ROMAIN ,  WILLIAM HUOTT ,  PAWEL OWCZARCZYK ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  CHUNG-LUNG SHUM ,  ALPER BUYUKTOSUNOGLU ,  TOBIAS WEBEL ,  MICHAEL CADIGAN JR ,  PAUL LOGSDON ,  SEAN CAREY ,  KARL ANDERSON ,  MARK CICHANOWSKI ,  STEFAN PAYER

IPC: H02H9/04 ,  G05F1/571 ,  H02H3/20

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. The method includes detecting a region, such as an individual processor, of a processor chip exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life. The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltage spikes back to within some pre-specified range. The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

公开(公告)号：GB2575412A

公开(公告)日：2020-01-08

申请号：GB201916132

申请日：2018-03-13

Applicant: IBM

Inventor： MICHAEL KARL GSCHWIND ,  CHUNG-LUNG SHUM ,  TIMOTHY SLEGEL ,  VALENTINA SALAPURA

IPC: G06F9/38

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

公开(公告)号：GB2581753B

公开(公告)日：2021-01-06

申请号：GB202008687

申请日：2018-11-08

Applicant: IBM

Inventor： NICHOLAS MATSAKIS ,  CRAIG WALTERS ,  JANE BARTIK ,  CHUNG-LUNG SHUM ,  ELPIDA TZORTZATOS

IPC: G06F12/0817 ,  G06F12/084

Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non-Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

公开(公告)号：GB2581753A

公开(公告)日：2020-08-26

申请号：GB202008687

申请日：2018-11-08

Applicant: IBM

Inventor： NICHOLAS MATSAKIS ,  CRAIG WALTERS ,  JANE BARTIK ,  CHUNG-LUNG SHUM ,  ELPIDA TZORTZATOS

IPC: G06F12/0817 ,  G06F12/084

Abstract: A shared cache line is concurrently modified by multiple processors of a computing environment. The concurrent modification is performed based, at least, on receiving one or more architected instructions (Fetch due to Non- Coherent Store instructions) that permit multiple processors to concurrently update the shared cache line absent obtaining a lock or having exclusive ownership of the data.

公开(公告)号：GB2630482A

公开(公告)日：2024-11-27

申请号：GB202411351

申请日：2023-01-09

Applicant: IBM

Inventor： LIOR BINYAMINI ,  LUDMILA ZERNAKOV ,  MARKUS KALTENBACH ,  CHUNG-LUNG SHUM ,  JANG-SOO LEE

IPC: G06F9/50 ,  G06F9/30

Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.

公开(公告)号：GB2575412B

公开(公告)日：2021-10-20

申请号：GB201916132

申请日：2018-03-13

Applicant: IBM

Inventor： MICHAEL KARL GSCHWIND ,  CHUNG-LUNG SHUM ,  TIMOTHY SLEGEL ,  VALENTINA SALAPURA

IPC: G06F9/38

Abstract: A load request to restore a plurality of architected registers is obtained. Based on obtaining the load request, one or more architected registers of the plurality of architected registers are restored. The restoring uses a snapshot that maps architected registers to physical registers to replace one or more physical registers currently assigned to the one or more architected registers with one or more physical registers of the snapshot corresponding to the one or more architected registers.

公开(公告)号：GB2574956B

公开(公告)日：2020-05-20

申请号：GB201913452

申请日：2018-02-20

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  CHUNG-LUNG SHUM ,  COREY STAPPENBECK ,  DAVID ANDREW SCHROTER

IPC: G06F9/30

公开(公告)号：GB2574956A

公开(公告)日：2019-12-25

申请号：GB201913452

申请日：2018-02-20

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  CHUNG-LUNG SHUM ,  COREY STAPPENBECK ,  DAVID ANDREW SCHROTER

IPC: G06F9/30

Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.