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    Auxiliary branch prediction with usefulness tracking
    1.
    发明专利
    Auxiliary branch prediction with usefulness tracking 未知

    公开(公告)号：GB2562651A

    公开(公告)日：2018-11-21

    申请号：GB201811397

    申请日：2016-12-07

    Applicant: IBM

    Inventor： JAMES JOSEPH BONANNO ,  MICHAEL JOSEPH CADIGAN ,  MATTHIAS DIETMAR HEIZMANN ,  BRIAN ROBERT PRASKY

    IPC: G06F9/38

    Abstract: According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

    Bypassing memory access for a load instruction using instruction address mapping
    5.
    发明专利
    Bypassing memory access for a load instruction using instruction address mapping 未知

    公开(公告)号：GB2574956A

    公开(公告)日：2019-12-25

    申请号：GB201913452

    申请日：2018-02-20

    Applicant: IBM

    Inventor： BRIAN ROBERT PRASKY ,  CHUNG-LUNG SHUM ,  COREY STAPPENBECK ,  DAVID ANDREW SCHROTER

    IPC: G06F9/30

    Abstract: Systems, methods, and computer-readable media are disclosed for executing a predicted load that bypasses memory access for a load instruction. A first physical register that is predicted as storing a value to be loaded by the load instruction is identified and the value stored in the first physical register is copied to a second physical register for use by a consumer operation. A predicted store instruction corresponding to the load instruction is identified and a mapping table is accessed to obtain data associated with the predicted store instruction. The data is evaluated to determine whether the predicted load meets dependency constraints. As a result of execution of the predicted load, the consumer operation can utilize the data stored in the first physical register directly and bypass the cache memory access that would otherwise be required to execute the load instruction.

    Auxiliary branch prediction with usefulness tracking
    8.
    发明专利
    Auxiliary branch prediction with usefulness tracking 未知

    公开(公告)号：GB2562651B

    公开(公告)日：2019-04-10

    申请号：GB201811397

    申请日：2016-12-07

    Applicant: IBM

    Inventor： JAMES JOSEPH BONANNO ,  MICHAEL JOSEPH CADIGAN ,  MATTHIAS DIETMAR HEIZMANN ,  BRIAN ROBERT PRASKY

    IPC: G06F9/38

    Abstract: According to an aspect, management of auxiliary branch prediction in a processing system including a primary branch predictor and an auxiliary branch predictor is provided. A congruence class of the auxiliary branch predictor is located based on receiving a primary branch predictor misprediction indicator corresponding to a mispredicted target address of the primary branch predictor. An entry is identified in the congruence class having an auxiliary usefulness level set to a least useful level with respect to one or more other entries of the congruence class. Auxiliary data corresponding to the mispredicted target address is installed into the entry. The auxiliary usefulness level of the entry is reset to an initial value based on installing the auxiliary data.

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