公开(公告)号：GB2576288B

公开(公告)日：2022-09-28

申请号：GB201917044

申请日：2018-05-21

Applicant: IBM

Inventor： JANG-SOO LEE ,  CHRISTIAN JACOBI ,  CHRISTIAN ZOELLIN ,  DAVID LEE ,  JANE BARTIK ,  ANTHONY SAPORITO

IPC: G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.

公开(公告)号：GB2576288A

公开(公告)日：2020-02-12

申请号：GB201917044

申请日：2018-05-21

Applicant: IBM

Inventor： JANG-SOO LEE ,  CHRISTIAN JACOBI ,  CHRISTIAN ZOELLIN ,  DAVID LEE ,  JANE BARTIK ,  ANTHONY SAPORITO

IPC: G06F9/38

Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.