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公开(公告)号：GB2576288B
公开(公告)日：2022-09-28
申请号：GB201917044
申请日：2018-05-21
Applicant: IBM
Inventor： JANG-SOO LEE , CHRISTIAN JACOBI , CHRISTIAN ZOELLIN , DAVID LEE , JANE BARTIK , ANTHONY SAPORITO
IPC: G06F9/38
Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
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公开(公告)号：GB2630482A
公开(公告)日：2024-11-27
申请号：GB202411351
申请日：2023-01-09
Applicant: IBM
Inventor： LIOR BINYAMINI , LUDMILA ZERNAKOV , MARKUS KALTENBACH , CHUNG-LUNG SHUM , JANG-SOO LEE
Abstract: A computer-implemented method includes assigning a first group of one or more units of an instruction pipeline of a processor as a frontend group and assigning a second group of the one or more units of the instruction pipeline of the processor as a backend group. A frontend logout is performed to transfer one or more trace records from the first group to a trace controller during an in-memory trace of an instruction. A backend logout is performed to transfer one or more trace records from the second group to the trace controller during the in-memory trace of the instruction. A next instruction is started in the first group of the instruction pipeline before the backend logout completes.
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公开(公告)号：GB2576288A
公开(公告)日：2020-02-12
申请号：GB201917044
申请日：2018-05-21
Applicant: IBM
Inventor： JANG-SOO LEE , CHRISTIAN JACOBI , CHRISTIAN ZOELLIN , DAVID LEE , JANE BARTIK , ANTHONY SAPORITO
IPC: G06F9/38
Abstract: Embodiments of the present invention are directed to a computer-implemented method for generating and verifying hardware instruction traces including memory data contents. The method includes initiating an in-memory trace (IMT) data capture for a processor, the IMT data being an instruction trace collected while instructions flow through an execution pipeline of the processor. The method further includes capturing contents of architected registers of the processor by: storing the contents of the architected registers to a predetermined memory location, and causing a load-store unit (LSU) to read contents of the predetermined memory location.
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