公开(公告)号：AT403905T

公开(公告)日：2008-08-15

申请号：AT05823124

申请日：2005-07-18

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F9/46

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

公开(公告)号：AT407403T

公开(公告)日：2008-09-15

申请号：AT05802300

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

公开(公告)号：AT390667T

公开(公告)日：2008-04-15

申请号：AT03812611

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL ,  HOFSTEE HARM ,  JOHNS CHARLES ,  KAHLE JAMES ,  TRUONG THUONG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.