公开(公告)号：JP2006134324A

公开(公告)日：2006-05-25

申请号：JP2005313388

申请日：2005-10-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES ,  TRUONG THUONG

IPC: G06F12/08 ,  G06F12/12 ,  G06F13/12

CPC classification number: G06F12/0848 ,  G06F12/0875

Abstract: PROBLEM TO BE SOLVED: To store data into a portion of a cache or other fast memory without also writing it to main memory. SOLUTION: A method of storing data transferred from an I/O device, a network, or a disk into a portion of the cache or other fast memory, without also writing it to the main memory is provided. Further, the data is "locked" into the cache or other fast memory until it is loaded for use. The data remains in a locking cache until it is specifically overwritten under software control. In this embodiment, a processor can write data to the cache or other fast memory without writing it also to the main memory. The portion of the cache or other fast memory can be used as additional system memory. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：将数据存储到高速缓存或其他快速存储器的一部分中，而不将其写入主存储器。 提供了一种将从I / O设备，网络或磁盘传送的数据存储到高速缓存或其他快速存储器的一部分中的方法，而不将其写入主存储器。 此外，数据被“锁定”到高速缓存或其他快速存储器中，直到它被加载使用为止。 数据保留在锁定缓存中，直到在软件控制下被特别覆盖。 在本实施例中，处理器可以将数据写入高速缓存或其他快速存储器，而不将其写入主存储器。 高速缓存或其他快速存储器的部分可以用作额外的系统存储器。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：DE602005008747D1

公开(公告)日：2008-09-18

申请号：DE602005008747

申请日：2005-07-18

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES RAY ,  LIU PEICHUN PETER ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F9/46

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

公开(公告)号：AT407403T

公开(公告)日：2008-09-15

申请号：AT05802300

申请日：2005-07-06

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28

Abstract: A method, an apparatus, and a computer program are provided for controlling memory access. Direct Memory Access (DMA) units have become commonplace in a number of bus architectures. However, managing limited system resources has become a challenge with multiple DMA units. In order to mange the multitude of commands generated and preserve dependencies, embedded flags in commands or a barrier command are used. These operations then can control the order in which commands are executed so as to preserve dependencies.

公开(公告)号：AT403905T

公开(公告)日：2008-08-15

申请号：AT05823124

申请日：2005-07-18

Applicant: SONY COMPUTER ENTERTAINMENT INC ,  IBM

Inventor： DAY MICHAEL ,  JOHNS CHARLES ,  LIU PEICHUN ,  TRUONG THUONG ,  YAMAZAKI TAKESHI

IPC: G06F13/28 ,  G06F9/46

Abstract: The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

公开(公告)号：AT390667T

公开(公告)日：2008-04-15

申请号：AT03812611

申请日：2003-11-21

Applicant: IBM

Inventor： DAY MICHAEL ,  HOFSTEE HARM ,  JOHNS CHARLES ,  KAHLE JAMES ,  TRUONG THUONG ,  SHIPPY DAVID

IPC: G06F12/10 ,  G06F12/12

Abstract: Memory management in a computer system is improved by preventing a subset of address translation information from being replaced with other types of address translation information in a cache memory reserved for storing such address translation information for faster access by a CPU. This way, the CPU can identify the subset of address translation information stored in the cache.

公开(公告)号：HK1090451A1

公开(公告)日：2006-12-22

申请号：HK06112000

申请日：2006-11-01

Applicant: IBM

Inventor： DAY MICHAEL NORMAN ,  JOHNS CHARLES ,  TRUONG THUONG

IPC: G06F20090101