公开(公告)号：GB2577023A

公开(公告)日：2020-03-11

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：GB2578070B

公开(公告)日：2020-09-09

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2578070A

公开(公告)日：2020-04-15

申请号：GB202000445

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  AARON TSAI ,  CHRISTIAN JACOBI ,  ANTHONY SAPORITO ,  ULRICH MAYER

IPC: G06F12/0864 ,  G06F12/0811 ,  G06F12/0895 ,  G06F12/10

Abstract: Disclosed herein is a method for operating access to a cache memory via an effective address comprising a tag field and a cache line index field. The method comprises: splitting the tag field into a first group of bits and a second group of bits. The line index bits and the first group of bits are searched in the set directory. A set identifier is generated indicating the set containing the respective cache line of the effective address. The set identifier, the line index bits and the second group of bits are searched in the validation directory. In response to determining the presence of the cache line in the set based on the second searching, a hit signal is generated.

公开(公告)号：GB2633234A

公开(公告)日：2025-03-05

申请号：GB202416054

申请日：2023-03-30

Applicant: IBM

Inventor： ASHRAF ELSHARIF ,  RICHARD BRANCIFORTE ,  GREGORY ALEXANDER ,  DEANNA POSTLES DUNN BERGER ,  TIMOTHY BRONSON ,  AARON TSAI ,  TAYLOR PRITCHARD ,  MARKUS KALTENBACH ,  CHRISTIAN JACOBI ,  MICHAEL BLAKE

IPC: G06F12/0811 ,  G06F12/0897

Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.

公开(公告)号：GB2577845B

公开(公告)日：2020-09-23

申请号：GB202000470

申请日：2018-06-14

Applicant: IBM

Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

IPC: G06F12/0815

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：GB2577023B

公开(公告)日：2020-08-05

申请号：GB202000046

申请日：2018-06-14

Applicant: IBM

Inventor： MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  CHISTIAN JACOBI ,  AARON TSAI ,  JOHANNES CHRISTIAN REICHART ,  MARKUS MICHAEL HELMS ,  ULRICH MAYER

IPC: G06F12/0842 ,  G06F12/0808 ,  G06F12/10

Abstract: Disclosed herein is a virtual cache and method in a processor for supporting multiple threads on the same cache line. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a corresponding tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and a per thread validity bit for each thread that accesses the cache line. When a subsequent thread determines that the cache line is valid for that thread the validity bit for that thread is set, while not invalidating any validity bits for other threads.

公开(公告)号：GB2574171B

公开(公告)日：2020-04-22

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2577845A

公开(公告)日：2020-04-08

申请号：GB202000470

申请日：2018-06-14

Applicant: IBM

Inventor： CHRISTIAN ZOELLIN ,  CHRISTIAN JACOBI ,  CHUNG-LUNG K SHUM ,  MARTIN RECKTENWALD ,  ANTHONY SAPORITO ,  AARON TSAI

IPC: G06F12/0815

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：GB2574171A8

公开(公告)日：2019-12-04

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.

公开(公告)号：GB2574171A

公开(公告)日：2019-11-27

申请号：GB201914312

申请日：2018-02-27

Applicant: IBM

Inventor： GREGORY WILLIAM ALEXANDER ,  SOMIN SONG ,  BRIAN DAVID BARRICK ,  ANTHONY SAPORITO ,  CHRISTIAN JACOBI ,  AARON TSAI ,  THOMAS WINTERS FOX

IPC: G06F9/38 ,  G06F12/0811

Abstract: A simultaneous multithread (SMT) processor having a shared dispatch pipeline includes a first circuit that detects a cache miss thread. A second circuit determines a first cache hierarchy level at which the detected cache miss occurred. A third circuit determines a Next To Complete (NTC) group in the thread and a plurality of additional groups (X) in the thread. The additional groups (X) are dynamically configured based on the detected cache miss. A fourth circuit determines whether any groups in the thread are younger than the determined NTC group and the plurality of additional groups (X), and flushes all the determined younger groups from the cache miss thread.