公开(公告)号：WO2009000639A3

公开(公告)日：2009-05-28

申请号：PCT/EP2008057199

申请日：2008-06-10

Applicant: IBM ,  IBM UK ,  ALVES LUIZ ,  CLARKE WILLIAM ,  DELL TIMOTHY ,  DEWKETT THOMAS ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS ,  O CONNOR JAMES

Inventor： ALVES LUIZ ,  CLARKE WILLIAM ,  DELL TIMOTHY ,  DEWKETT THOMAS ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS ,  O CONNOR JAMES

IPC: G06F11/10

CPC classification number: G06F11/108 ,  G06F2211/1045 ,  G06F2211/1057 ,  G06F2211/1064

Abstract: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

Abstract translation: 一种用于存储系统中的纠错和检测的系统和方法。 该系统包括存储器控制器，多个存储器模块和机构。 存储器模块与存储器控制器和多个存储器件通信。 该机制检测到其中一个内存模块出现故障，可能与其他内存模块上的内存设备故障一致。 该机制允许内存系统在内存模块故障和内存设备故障的情况下继续运行不受损坏。

公开(公告)号：WO2010000623A3

公开(公告)日：2010-02-25

申请号：PCT/EP2009057580

申请日：2009-06-18

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

Inventor： DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

IPC: G06F11/00

CPC classification number: H04L1/0056 ,  G06F11/10

Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

Abstract translation: 一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。 该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信，并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。 下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。 下行CRC比特能够检测到车道故障，转移故障和高达五位随机错误中的任何一个。

公开(公告)号：WO2010000623A4

公开(公告)日：2010-04-22

申请号：PCT/EP2009057580

申请日：2009-06-18

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

Inventor： DELL TIMOTHY ,  GOWER KEVIN ,  LASTRAS-MONTANO LUIS

IPC: G06F11/00

CPC classification number: H04L1/0056 ,  G06F11/10

Abstract: A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.

Abstract translation: 一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。 该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。 下游链路与存储器控制器和存储器集线器设备通信并且包括至少十三条信道，用于从存储器控制器向存储器集线器设备传输多传送下游帧。 下游帧的一部分包括下游CRC比特以检测下游帧中的错误。 下行CRC位能够检测到通道故障，传输故障和高达5位随机错误中的任何一个。

公开(公告)号：AT478486T

公开(公告)日：2010-09-15

申请号：AT07821012

申请日：2007-10-08

Applicant: IBM

Inventor： DELL TIMOTHY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x10+x3+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x6+1.