公开(公告)号：WO2008052858B1

公开(公告)日：2008-07-31

申请号：PCT/EP2007060639

申请日：2007-10-08

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY JAY ,  GLAISE RENE

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

CPC classification number: H04L25/03866 ,  H03M13/03 ,  H03M13/27 ,  H04L1/0042 ,  H04L1/0057 ,  H04L1/0071

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x 10 + x 3 + 1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x) = x 6 + 1.

Abstract translation: 前向纠错（FEC）码与64B / 66B编码标准在串行器/解串器（SerDes）通信链路上传输时使用的自同步扰码器兼容。 FEC码允许编码和解码分别在加扰之前和之后发生，以便保持对发送信号的加扰操作的属性。 尽管由于64B / 66B加扰过程导致的所有传输错误的三倍，该代码仍允许纠正任何单个传输错误。 汉明码与度为n的比特交织奇偶校验码（BIP-n）组合。 这两个代码既提供了对数据包最大长度的任何错误的保护，也提供了通过解扰过程复制两次或三次的错误的保护。 所有单比特错误，无论是否倍增，都具有独特的综合征，因此易于纠正。 另外，数据包可以通过多个串行链路传输，以实现更高带宽应用，而不会降低代码效率。 汉明码可以由任何不可约多项式产生，例如H（x）= x 10 + x 3 + 1 + BIP码被选择为6度 以适合64B / 66B加扰多项式并由B（x）= x + 6 + 1表示。

公开(公告)号：WO2008052858A2

公开(公告)日：2008-05-08

申请号：PCT/EP2007060639

申请日：2007-10-08

Applicant: IBM ,  IBM UK ,  DELL TIMOTHY JAY ,  GLAISE RENE

Inventor： DELL TIMOTHY JAY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

CPC classification number: H04L25/03866 ,  H03M13/03 ,  H03M13/27 ,  H04L1/0042 ,  H04L1/0057 ,  H04L1/0071

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x) = x 10 + x 3 + 1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x) = x 6 + 1.

公开(公告)号：JPH10178353A

公开(公告)日：1998-06-30

申请号：JP29220197

申请日：1997-10-24

Applicant: IBM

Inventor： GLAISE RENE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00

Abstract: PROBLEM TO BE SOLVED: To reduce the time for a pay road FCS(frame inspection sequence) and for the inspection of a cell pay road FCS by calculating the CRC(circulating redundancy inspection) code of an input bit stream through the use of the polynominal of a degree being the multiple of a generated polynominal. SOLUTION: A logical block 12 is applied to an input bit stream 10 read by each one byte and the polynominal divisor of a degree 123. The remainder of division by M123, namely the first division of FSC calculation, is a polynominal not more than a degree 122 to be written into a 123-bit register 14. Then a 123-bit stream is inputted to a combination array 16 realizing the polynominal division of a 123 bit stream by the generated polynominal of a degree 32. The result of second division is a polynomial not more than a degree 31 expressing a 32-bit stream written in a 32 bit register 18. Two times of consecutive polynominal division is executed instead of polynominal division by G like this.

公开(公告)号：DE3782500D1

公开(公告)日：1992-12-10

申请号：DE3782500

申请日：1987-12-23

Applicant: IBM

Inventor： GLAISE RENE ,  HARTMANN YVES ,  HUON PIERRE ,  PEYRONNENC MICHEL

IPC: G06F13/16 ,  G06F13/18 ,  G06F13/42

Abstract: The interface mechanism provides one memory request line (11, 12) for each user device and which is activated by the user device when it requests an access to the memory to effect a memory read or write transfer. A last operation line (30), shared by the user devices, is activated by the user device when its memory transfer is complete. An address user indicator line (15,16) and a data user indicator line (17,18) are provided for each user device. An address clock line (26) and a data clock line (28) are shared by the user devices. A memory interface controller (5) responds to the status of memory request lines to select a request from a user device, and to activate the address user and data user indicator lines of the selected device during the periods when the selected device may use the address, data bus. In addition, the controller sends clock pulses for timing transfer of the address and data signals on the respective bus. User interface controls (3-1, 3-2) respond to the controller clock pulses.

公开(公告)号：DE69731932T2

公开(公告)日：2006-02-16

申请号：DE69731932

申请日：1997-08-19

Applicant: IBM

Inventor： GLAISE RENE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00

Abstract: A method and an apparatus to calculate the CRC-32 (Cyclic Redundancy Checking) codes of a bit stream while improving the process time and simple to implement. The CRC-32 calculation is used for FCS (Frame Check Sequence) error checking code of bit stream messages sent over a fixed size packet networks when the high speeds require reducing the processing time in the network access nodes. This CRC-32 calculation is also used for FCS checking in the network equipment receiving said packetized bit stream messages. This invention applies particularly to messages conveyed via AAL5 type cells in ATM networks. The CRC-32 per byte computation of the prior art is replaced by a simple per byte CRC-R computation followed by a one pass CRC-32 computation of the R bit stream, result of the CRC-R computation. The CRC-R codes being generated by a M(X), a polynomial of degree R, multiplier of the generator polynomial of degree 32,the generator of the Galois Field constituting the CRC-32 codes.

公开(公告)号：DE69841981D1

公开(公告)日：2010-12-16

申请号：DE69841981

申请日：1998-09-16

Applicant: IBM

Inventor： GLAISE RENE ,  PORET MICHEL

IPC: H04Q11/04 ,  H04L49/111

公开(公告)号：AT478486T

公开(公告)日：2010-09-15

申请号：AT07821012

申请日：2007-10-08

Applicant: IBM

Inventor： DELL TIMOTHY ,  GLAISE RENE

IPC: H04L1/00 ,  H04L25/03

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable. In addition, the packet can be transported across multiple serial links for higher bandwidth applications without a degradation of the code efficiency. The Hamming code can be generated from any irreducible polynomial, such as H(x)=x10+x3+1. The BIP code is chosen to be of degree 6 to fit with 64B/66B scrambling polynomial and is represented by B(x)=x6+1.

公开(公告)号：DE69731932D1

公开(公告)日：2005-01-20

申请号：DE69731932

申请日：1997-08-19

Applicant: IBM

Inventor： GLAISE RENE

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H03M13/15 ,  H04L1/00

Abstract: A method and an apparatus to calculate the CRC-32 (Cyclic Redundancy Checking) codes of a bit stream while improving the process time and simple to implement. The CRC-32 calculation is used for FCS (Frame Check Sequence) error checking code of bit stream messages sent over a fixed size packet networks when the high speeds require reducing the processing time in the network access nodes. This CRC-32 calculation is also used for FCS checking in the network equipment receiving said packetized bit stream messages. This invention applies particularly to messages conveyed via AAL5 type cells in ATM networks. The CRC-32 per byte computation of the prior art is replaced by a simple per byte CRC-R computation followed by a one pass CRC-32 computation of the R bit stream, result of the CRC-R computation. The CRC-R codes being generated by a M(X), a polynomial of degree R, multiplier of the generator polynomial of degree 32,the generator of the Galois Field constituting the CRC-32 codes.

公开(公告)号：DE68916945D1

公开(公告)日：1994-08-25

申请号：DE68916945

申请日：1989-04-28

Applicant: IBM

Inventor： HUON PIERRE ,  GLAISE RENE

IPC: G06F15/16 ,  G06F5/10 ,  G06F12/00 ,  G06F13/42 ,  G06F15/177 ,  H04L7/00 ,  G06F5/06

公开(公告)号：DE68916945T2

公开(公告)日：1995-03-16

申请号：DE68916945

申请日：1989-04-28

Applicant: IBM

Inventor： HUON PIERRE ,  GLAISE RENE

IPC: G06F15/16 ,  G06F5/10 ,  G06F12/00 ,  G06F13/42 ,  G06F15/177 ,  H04L7/00 ,  G06F5/06