METHOD FOR MEASURING THE REAL CONTACT AREA IN CONNECTORS

    公开(公告)号:DE3570743D1

    公开(公告)日:1989-07-06

    申请号:DE3570743

    申请日:1985-03-29

    Applicant: IBM

    Abstract: A method to measure the real contact surface area of a connector or pin is disclosed. The pin and the connector is Gold plated. The pin or the connector is coated with platinum. The pin surface and the connector surface actually comprise a multitude of peaks and valleys, termed asperites. If the pin is chosen to be coated with the platinum, the platinum coated pin is mated with a connector. A portion of the pin surface contacts a corresponding portion of the connector surface. The portion of the pin surface and the corresponding portion of the connector surface is termed a real contact surface area. The pin and connector are separated. The platinum formerly adhering to the real contact surface area of the pin is removed and adheres to the real contact surface of the gold plated connector. Using a metallograph or a scanning electron microscope, the real contact surface of the connector or pin is studied and observed. Since the visual image of platinum is substantially different than the visual image of Gold, the real contact surface area of the pin (and of the connector) is readily discernable. Using an image analyzer, the real contact surface area on the pin and on the connector is measured.

    2.
    发明专利
    未知

    公开(公告)号:DE3881543D1

    公开(公告)日:1993-07-15

    申请号:DE3881543

    申请日:1988-03-01

    Applicant: IBM

    Abstract: A method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier (2) on a second level electronic package, such that the flexible film (6) of the carrier is supported substantially in a plane above the surface of the second level electronic package. The method comprises positioning preformed spacers (10) embedded in a dissolvable polysulfone foam holder (18) between the outer lead bonding pads (11) on the flexible film semiconductor chip carrier and corresponding (matching) bonding pads (12) on the second level electronic package. Each of the preformed spacers may comprise, for example, a solder cylinder with a copper core. The preformed spacers may be bonded to the outer lead bonding pads on the chip carrier, and to the matching bonding pads on the second level electronic package, by reflowing the solder of the spacers using, for example, a conventional solder reflow oven. Then, the holder (18) is dissolved, and washed away, in a conventional vapor degreaser using, for example, methylene chloride, to leave the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.

    3.
    发明专利
    未知

    公开(公告)号:DE3881543T2

    公开(公告)日:1993-12-23

    申请号:DE3881543

    申请日:1988-03-01

    Applicant: IBM

    Abstract: A method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier (2) on a second level electronic package, such that the flexible film (6) of the carrier is supported substantially in a plane above the surface of the second level electronic package. The method comprises positioning preformed spacers (10) embedded in a dissolvable polysulfone foam holder (18) between the outer lead bonding pads (11) on the flexible film semiconductor chip carrier and corresponding (matching) bonding pads (12) on the second level electronic package. Each of the preformed spacers may comprise, for example, a solder cylinder with a copper core. The preformed spacers may be bonded to the outer lead bonding pads on the chip carrier, and to the matching bonding pads on the second level electronic package, by reflowing the solder of the spacers using, for example, a conventional solder reflow oven. Then, the holder (18) is dissolved, and washed away, in a conventional vapor degreaser using, for example, methylene chloride, to leave the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired.

    4.
    发明专利
    未知

    公开(公告)号:DE3871996T2

    公开(公告)日:1993-01-14

    申请号:DE3871996

    申请日:1988-03-01

    Applicant: IBM

    Abstract: Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier (2) on a second level electronic package (4). The resulting electronic packaging structure includes electrically conductive spacers (10), such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads (11) on the flexible film semiconductor chip carrier and corresponding bonding pads (12) on the second level electronic package, and which physically support the flexible film (6) of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture (30) comprising a base plate (32), a pressure insert (34) with a resilient member (37), and a top plate (36). The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template (15) having a pattern of openings (27) corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.

    5.
    发明专利
    未知

    公开(公告)号:DE3871996D1

    公开(公告)日:1992-07-23

    申请号:DE3871996

    申请日:1988-03-01

    Applicant: IBM

    Abstract: Method and apparatus are disclosed for mounting a flexible film semiconductor chip carrier (2) on a second level electronic package (4). The resulting electronic packaging structure includes electrically conductive spacers (10), such as solder balls or solder coated copper balls, which electrically interconnect outer lead bonding pads (11) on the flexible film semiconductor chip carrier and corresponding bonding pads (12) on the second level electronic package, and which physically support the flexible film (6) of the semiconductor chip carrier substantially in a plane above the surface of the second level electronic package. This electronic packaging structure is made using a special assembly fixture (30) comprising a base plate (32), a pressure insert (34) with a resilient member (37), and a top plate (36). The flexible film semiconductor chip carrier with the spacers attached thereto is placed over the resilient member of the pressure insert which is clamped together with the second level electronic package between the top and base plates. Then, this assembly is heated to reflow the solder of the spacers, and the assembly fixture is disassembled, leaving the flexible film semiconductor chip carrier mounted on the second level electronic package with the flexible film of the carrier having a planar geometry as desired. The spacers may be attached to the flexible film semiconductor chip carrier using a special template (15) having a pattern of openings (27) corresponding to the pattern of outer lead bonding pads on the flexible film semiconductor chip carrier.

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