PLASMA ETCHING REACTOR WITH REDUCED PLASMA POTENTIAL

    公开(公告)号:CA1219975A

    公开(公告)日:1987-03-31

    申请号:CA504804

    申请日:1986-03-24

    Applicant: IBM

    Abstract: PLASMA ETCHING REACTOR WITH REDUCED PLASMA POTENTIAL An improved plasma reactor for uniformly etching a large number of semiconductor wafers at a reduced plasma potential includes, in one embodiment, a grounded plate mounted intermediate the cathode and the top plate of a reactor chamber, the top plate and the chamber walls forming the reactor anode. The grounded plate is spaced apart from the chamber top plate a distance sufficient to allow a plasma to be established between the grounded plate and the top plate, and the distance between the grounded plate and the cathode is large enough not to disturb the field in the proximity of the wafers being etched. The plate can be apertured to facilitate etchant gas flow. According to another embodiment of the invention at least two grounded plates are employed, spaced apart from each other and from the upper surface of the reactor plasma chamber.

    LATERAL TRANSISTOR AND METHOD OF MAKING SAME

    公开(公告)号:CA2007412C

    公开(公告)日:1995-01-17

    申请号:CA2007412

    申请日:1990-01-09

    Applicant: IBM

    Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bounding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.

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