公开(公告)号：DE69018499D1

公开(公告)日：1995-05-18

申请号：DE69018499

申请日：1990-01-19

Applicant: IBM

Inventor： HABITZ PETER-ANTON ,  HSIEH CHANG-MING ,  HUANG YI-SHIOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: A process of forming a lateral PNP transistor that includes the steps of: providing a chip of semicon-ductor material including an isolated N- device region (14) over a P substrate (16), with an N-epitaxial layer (20), a N+ buried subcollector (18), and a reach-through region (26); implanting N dopant material at a relatively low power and low dosage into a selected implant region (32), of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region to form emitter and collector regions (34,36) in the device region such that an intrinsic base region (38), is defined there-between.

公开(公告)号：DE69018499T2

公开(公告)日：1995-11-09

申请号：DE69018499

申请日：1990-01-19

Applicant: IBM

Inventor： HABITZ PETER-ANTON ,  HSIEH CHANG-MING ,  HUANG YI-SHIOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10

Abstract: A process of forming a lateral PNP transistor that includes the steps of: providing a chip of semicon-ductor material including an isolated N- device region (14) over a P substrate (16), with an N-epitaxial layer (20), a N+ buried subcollector (18), and a reach-through region (26); implanting N dopant material at a relatively low power and low dosage into a selected implant region (32), of the device region; implanting N dopant material at a relatively higher power and higher dosage into the implant region to form emitter and collector regions (34,36) in the device region such that an intrinsic base region (38), is defined there-between.

公开(公告)号：DE69223193T2

公开(公告)日：1998-05-20

申请号：DE69223193

申请日：1992-07-10

Applicant: IBM

Inventor： HSIEH CHANG-MING ,  KUMAR SHANTHA ARAKERE ,  HSU LOUIS LU-CHEN ,  TIEN ZU-JEAN TIEN ZU-JEAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

Abstract: A mesa comprising successive layers of bottom SiO2 (22A/32), polysilicon pad (22A), top silicon nitride (26A) is first formed on a semiconductor substrate (20). Next, a first layer (34) of N type polysilicon and a second layer (36) of silicon nitride are conformally deposited thereon. Next, the said second layer is anisotropically etched to leave sidewall spacers (36A). A portion of said first layer at the top of the mesa is now exposed. The said exposed portion is then removed leaving lateral sidewalls (34A), whose top part are oxidized (38). Next, all the silicon nitride material is removed exposing the polysilicon pad (22A) and leaving very narrow sidewall spacers (34A) of N type polysilicon that are used as in-situ masks to deliverate very sub-micronic portions (32A) of the bottom SiO2 layer to be subsequently used as the gate dielectric for the FETs.

公开(公告)号：DE69223193D1

公开(公告)日：1998-01-02

申请号：DE69223193

申请日：1992-07-10

Applicant: IBM

Inventor： HSIEH CHANG-MING ,  KUMAR SHANTHA ARAKERE ,  HSU LOUIS LU-CHEN ,  TIEN ZU-JEAN TIEN ZU-JEAN

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78

Abstract: A mesa comprising successive layers of bottom SiO2 (22A/32), polysilicon pad (22A), top silicon nitride (26A) is first formed on a semiconductor substrate (20). Next, a first layer (34) of N type polysilicon and a second layer (36) of silicon nitride are conformally deposited thereon. Next, the said second layer is anisotropically etched to leave sidewall spacers (36A). A portion of said first layer at the top of the mesa is now exposed. The said exposed portion is then removed leaving lateral sidewalls (34A), whose top part are oxidized (38). Next, all the silicon nitride material is removed exposing the polysilicon pad (22A) and leaving very narrow sidewall spacers (34A) of N type polysilicon that are used as in-situ masks to deliverate very sub-micronic portions (32A) of the bottom SiO2 layer to be subsequently used as the gate dielectric for the FETs.

公开(公告)号：CA2007412C

公开(公告)日：1995-01-17

申请号：CA2007412

申请日：1990-01-09

Applicant: IBM

Inventor： DESILETS BRIAN H ,  HSIEH CHANG-MING ,  HSU LOUIS L C

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L29/735 ,  H01L21/461

Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bounding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.