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公开(公告)号：US3645392A
公开(公告)日：1972-02-29
申请号：US3645392D
申请日：1970-08-26
Applicant: IBM
Inventor： CHITTENDEN RUDY M , DESKEVICH STEPHEN , PLUMMER NORMAN R , ROHRER GENE D , ZAMAN LOUIS F
Abstract: A magnetic ink character reader/sorter having improved means for processing the character signals, storing the pocket selection control signals derived therefrom, and checking the overall operation of the machine. The documents are read by an improved single-gap recognition system, and the sorting information derived therefrom is supplied to a plurality of buffers in accordance with control signals derived from the motion of a document transport.
Abstract translation: 一种具有改进的用于处理字符信号的装置的磁性墨水字符读取器/分类器，存储从其导出的口袋选择控制信号，以及检查机器的整体操作。 通过改进的单间隙识别系统读取文档，并且根据从文档传送的运动导出的控制信号将从其导出的排序信息提供给多个缓冲器。
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公开(公告)号：US3492655A
公开(公告)日：1970-01-27
申请号：US3492655D
申请日：1966-12-30
Applicant: IBM
Inventor： DESKEVICH STEPHEN , NEWMAN JOHN B
CPC classification number: G06F7/4912 , G06F15/02 , G06F2207/49185 , G06Q20/042 , G06Q40/02 , G11C21/00
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公开(公告)号：US3882358A
公开(公告)日：1975-05-06
申请号：US37384873
申请日：1973-06-26
Applicant: IBM
Inventor： DESKEVICH STEPHEN , PEACOCK JAMES C , TYNAN RICHARD F , WILSON ALAN D
CPC classification number: H05B41/30
Abstract: Charging circuit for a flash lamp in which flash holdover is prevented by establishing a high impedance charging circuit for a predetermined time after flash initiation to allow deionization of the lamp plasma and, after a predetermined time, establishing a low impedance charging circuit to provide a fast charging rate for the energy storage device. Impedance levels are changed in the circuit by gating a silicon controlled rectifier (SCR) with a control signal a predetermined time after flash initiation so as to bypass a high impedance circuit path in parallel therewith. As the energy storage device becomes fully charged, the SCR returns to its blocking condition, the control signal terminates and the lamp can be fired again.
Abstract translation: 用于闪光灯的充电电路，其中通过在闪光开始之后建立高阻抗充电电路达预定时间来防止闪光灯保持，以允许灯等离子体去离子，并且在预定时间之后建立低阻抗充电电路以提供快速 储能装置的充电率。 通过在闪光开始之后的预定时间内通过控制信号选通可控硅整流器（SCR），以便与其并联的高阻抗电路路径旁路，在电路中改变阻抗水平。 当能量存储装置充满电时，SCR返回到其阻塞状态，控制信号终止并且灯可以再次点火。
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公开(公告)号：US3462411A
公开(公告)日：1969-08-19
申请号：US3462411D
申请日：1966-12-23
Applicant: IBM
Inventor： DESKEVICH STEPHEN , NEWMAN JOHN B
CPC classification number: G11C21/00
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公开(公告)号：CA819917A
公开(公告)日：1969-08-05
申请号：CA819917D
Applicant: IBM
Inventor： NEWMAN JOHN B , DESKEVICH STEPHEN
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Patent Agency Ranking
公开(公告)号：DE2422201A1
公开(公告)日：1975-01-16
申请号：DE2422201
申请日：1974-05-08
Applicant: IBM
Abstract: Charging circuit for a flash lamp in which flash holdover is prevented by establishing a high impedance charging circuit for a predetermined time after flash initiation to allow deionization of the lamp plasma and, after a predetermined time, establishing a low impedance charging circuit to provide a fast charging rate for the energy storage device. Impedance levels are changed in the circuit by gating a silicon controlled rectifier (SCR) with a control signal a predetermined time after flash initiation so as to bypass a high impedance circuit path in parallel therewith. As the energy storage device becomes fully charged, the SCR returns to its blocking condition, the control signal terminates and the lamp can be fired again.
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公开(公告)号：CA946074A
公开(公告)日：1974-04-23
申请号：CA119486
申请日：1971-07-30
Applicant: IBM
Inventor： CHITTENDEN RUDY M , DESKEVICH STEPHEN , ROHRER GENE D , ZAMAN LOUIS F III , PLUMMER NORMAN R
Abstract: A magnetic ink character reader/sorter having improved means for processing the character signals, storing the pocket selection control signals derived therefrom, and checking the overall operation of the machine. The documents are read by an improved single-gap recognition system, and the sorting information derived therefrom is supplied to a plurality of buffers in accordance with control signals derived from the motion of a document transport.
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公开(公告)号：DE1549488A1
公开(公告)日：1971-04-01
申请号：DE1549488
申请日：1967-12-28
Applicant: IBM
Inventor： DESKEVICH STEPHEN , BERDEMUS NEWMAN JOHN
Abstract: 1,196,260. Digital calculators; delay line stores. INTERNATIONAL BUSINESS MACHINES CORP. 20 Dec., 1967 [30 Dec., 1966], No. 57990/67. Headings G4A and G4C. In data processing apparatus, a keyboard feeds a one-field "entry" recirculating delay line store, and a timing ring selects a field of a multifield "main" recirculating delay line store, the contents of the entry store and the selected field of the main store being added and the result inserted into the selected field of the main store. In a bank machine, decimal digits from a keyboard (entered high order first) are coded in BCD form by OR gates, stored in entry latches, then serialized by gates and inserted into a recirculating entry delay line loop. The loop comprises a delay line capable of holding a field of ten digits, retiming triggers, and a one-digit shift register which is normally by-passed. Arrival of a digit in the entry latches causes digits already in the loop to be recirculated via the shift register for one revolution and the new digit to be inserted in front of them in the loop. A "double zero" key on the keyboard causes zero to be entered twice, by delaying reset of the entry latches (which normally occurs after each digit) until a zero entered into them has been inserted into the delay loop twice. The field in the entry delay loop can be passed low order first, serially by digit, parallel by bit, from the shift register to an adder to be added to any of twenty fields from a main delay loop, this loop comprising a delay line and a one-digit shift register for supplying the field to the adder in serial-parallel form. Manual selector keys controlling latches which control pluggable programme cards can select main loop fields for this, and the stackers to which cheques are to be directed. The adder comprises in order: conversion from BCD to qui-binary (by gates), complementing of the main loop operand digits if the operand signs are different or if a subtraction is required (e.g. to check a sum of cheque amounts against a deposit slip total), qui-binary addition, conversion from qui-binary to BCD, latching of the result digit, and serializing (by gates) for insertion of the result into the main loop source field. When complementing took place, recomplementing or end-around add follows as necessary, utilizing a marker bit stored in the main loop. The various main loop fields can be printed out, on three printers, in response to keys or detection of non-balance in the check referred to. Marker bits may be stored in the main loop to indicate fields already printed when a sequence of fields is being printed. The delay lines may be of the magnetostrictive or sonic type. Specification 1,196,259 is referred to.
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公开(公告)号：CA886229A
公开(公告)日：1971-11-16
申请号：CA886229D
Applicant: IBM
Inventor： NEWMAN JOHN B , DESKEVICH STEPHEN
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公开(公告)号：DE1549487A1
公开(公告)日：1971-01-21
申请号：DE1549487
申请日：1967-12-28
Applicant: IBM
Inventor： DESKEVICH STEPHEN , BERDEMUS NEWMAN JOHN
Abstract: 1,196,259. Digital calculators; delay line stores. INTERNATIONAL BUSINESS MACHINES CORP. 13 Dec., 1967 [23 Dec., 1966], No. 56945/67. Headings G4A and G4C. Data processing apparatus comprises a delay line recirculating store, input means to enter data into a first of its time slots, and shifting means including a register connected in the loop to shift stored data along the sequence of time slots, the data items entering the register serially by bit, and means for reading each item of data from the register parallel by bit. A decimal number is entered high order first by pressing decimal digit keys on a keyboard, each digit being coded into BCD form by OR gates, stored in entry latches, then serialized by gates and entered into the recirculating delay loop. The delay loop comprises a magnetostrictive or sonic delay line capable of holding a field of ten digits, retiming triggers, and a one-digit shift register which is normally bypassed. Arrival of a digit in the entry latches causes digits already in the loop to be recirculated via the shift register for one revolution and the new digit to be inserted in front of them in the loop. The digits can be passed low order first, serially by digit, parallel by bit, from the shift register to an arithmetic unit to be used for updating fields in a main delay line. The keyboard includes a "double zero" key which causes two zeros to be entered, by delaying reset of the entry latches (which normally occurs after each digit) so that the same zero is entered into the delay loop twice.
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