公开(公告)号：JP2007142401A

公开(公告)日：2007-06-07

申请号：JP2006303404

申请日：2006-11-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DOMINIC J SCHEPIS ,  LEE JUNEDONG ,  DEVENDRA K SADANA ,  SHAHIDI GHAVAM G

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/20 ,  H01L23/52 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/76251 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/04

Abstract: PROBLEM TO BE SOLVED: To provide a substrate for semiconductor device including a plurality of semiconductor-on-insulator (SOI) wafers that are coupled with each other in a single stack. SOLUTION: The remote end of this stack includes a first SOI region with a first semiconductor layer of a certain thickness having a first surface orientation. The surface of this single stack can further comprise a non-SOI region or at least a second SOI region, or comprise both of them. This non-SOI region can comprise a bulk silicon extending through all insulator layers of the single stack and having a thickness different from that of a first silicon layer. A second SOI region has a second semiconductor layer having a thickness different from that of the first semiconductor layer or the surface orientation different from the first surface orientation, or both different. Thus, this substrate can permit the formation of different devices on the optimum substrate region with the different surface orientation, the different thickness, the different structure from the bulk or SOI, or the combination of these different ones. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种包括在单个堆叠中彼此耦合的多个绝缘体上半导体（SOI）晶片的半导体器件的衬底。 解决方案：该堆叠的远端包括具有第一表面取向的具有一定厚度的第一半导体层的第一SOI区域。 该单个堆叠的表面可以进一步包括非SOI区域或至少第二SOI区域，或者包括它们两者。 该非SOI区域可以包括延伸穿过单个堆叠的所有绝缘体层并且具有与第一硅层的厚度不同的厚度的体硅。 第二SOI区域具有与第一半导体层的厚度不同的第二半导体层或与第一表面取向不同的表面取向，或者两者不同。 因此，该衬底可以允许在最佳衬底区域上形成不同的器件，其具有不同的表面取向，不同的厚度，与本体或SOI的不同结构，或这些不同的组合。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：GB2600544B

公开(公告)日：2023-01-11

申请号：GB202113289

申请日：2021-09-17

Applicant: IBM

Inventor： NING LI ,  JOEL P DE SOUZA ,  KEVIN W BREW ,  DEVENDRA K SADANA

IPC: G11C11/56 ,  G11C13/00

Abstract: A Phase-Change Memory (PCM) device includes a dielectric layer, a bottom electrode disposed in the dielectric layer, a liner material disposed on the bottom electrode, a phase-change material disposed on the liner material, and a top electrode disposed on the phase-change material and in the dielectric layer.

公开(公告)号：IL297602A

公开(公告)日：2022-12-01

申请号：IL29760222

申请日：2022-10-24

Applicant: IBM ,  NING LI ,  DEVENDRA K SADANA

Inventor： NING LI ,  DEVENDRA K SADANA

IPC: G11C11/56 ,  G11C13/00 ,  H01L45/00

Abstract: According to some embodiments of the present invention a phase change device (PCD) has a first and second semiconductor layer. The first semiconductor layer made of a first semiconductor material and has a first semiconductor thickness, a first interface surface, and a first electrode surface. The first interface surface and first electrode surface are on opposite sides of the first semiconductor layer. The first semiconductor material can transition between a first amorphous state and a first crystalline state at one or more first conditions. The second semiconductor layer is made of a second semiconductor material and has a second semiconductor thickness, a second interface surface, and a second electrode surface. The second interface surface and second electrode surface are on opposite sides of the second semiconductor layer. The first interface surface and the second interface surface are in electrical, physical, and chemical contact with one another at an interface. The second semiconductor material can transition between a second amorphous state and a second crystalline state at one or more second conditions. A first electrode in physical and electrical contact with the first electrode surface of the first semiconductor layer and a second electrode in physical and electrical contact with the second electrode surface of the second semiconductor layer. The first conditions and second conditions are different. Therefore, in some embodiments, the first and second semiconductor materials can be in different amorphous and/or crystalline states. The layers can have split amorphous/crystalline states. By controlling how the layers are split, the PCD can be in different resistive states.

公开(公告)号：GB2600544A

公开(公告)日：2022-05-04

申请号：GB202113289

申请日：2021-09-17

Applicant: IBM

Inventor： NING LI ,  JOEL P DE SOUZA ,  KEVIN W BREW ,  DEVENDRA K SADANA

IPC: G11C11/56 ,  G11C13/00 ,  H01L45/00

Abstract: A Phase-Change Memory (PCM) device 102 comprising a dielectric layer 206, bottom electrode 204 in dielectric layer, a liner material 203 on bottom electrode, a phase-change material 202, 205 on the liner material and a top electrode 201 on the phase-change material and in the dielectric layer. The liner material and phase change material PCM may be in the dielectric layer. The liner material may comprise a conductive oxide thin film such as Al doped ZnO (AZO), doped indium oxide with tin (ITO) or doped metal oxide. Alternatively the liner material may comprise a metal layer formed of Aluminium Al only or Al disposed over a conductive oxide thin film (e.g Al doped ZnO (AZO)).The dielectric layer may comprise several dielectric layers. Electrodes may comprise of metal nitride (TaN, TiN, WN). A method of manufacture is included. Alternative phase-change memory includes first electrode and second on first and second side respectively of dielectric layer, the phase-change material on dielectric layer and first and second electrodes, and a liner material disposed on the phase-change material (figure 7). Figure 8 is another embodiment. The liner may reduce resistance drift acting as an inert or thermal cap further reducing heat loss.