公开(公告)号：DE68921869D1

公开(公告)日：1995-04-27

申请号：DE68921869

申请日：1989-12-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F12/08 ,  G06F12/084 ,  G06F13/38

公开(公告)号：DE69023677D1

公开(公告)日：1996-01-04

申请号：DE69023677

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

公开(公告)号：DE68921869T2

公开(公告)日：1995-10-12

申请号：DE68921869

申请日：1989-12-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F12/08 ,  G06F12/084 ,  G06F13/38

公开(公告)号：DE69023677T2

公开(公告)日：1996-06-20

申请号：DE69023677

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F13/42

公开(公告)号：DE69021594T2

公开(公告)日：1996-05-02

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100T2

公开(公告)日：1995-10-05

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.

公开(公告)号：DE69021594D1

公开(公告)日：1995-09-21

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69018100D1

公开(公告)日：1995-05-04

申请号：DE69018100

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system is described which can transfer data between a master subsystem and a slave subsystem on bus address lines as well as bus data lines during a high speed data transfer. Data is clocked during the high speed transfer by a high speed clock signal which is separate from a normal bus clock signal. Data is transferred at the maximum rate which can be handled by both the master subsystem and the slave subsystem.