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    METHOD AND DEVICE FOR EXTENDED ERROR PROCESSING FOR I/O LOADING/STORING OPERATION ON PCI DEVICE BY ILLEGAL PARITY OR 0-BYTE ENABLING
    1.
    发明专利
    METHOD AND DEVICE FOR EXTENDED ERROR PROCESSING FOR I/O LOADING/STORING OPERATION ON PCI DEVICE BY ILLEGAL PARITY OR 0-BYTE ENABLING 失效

    公开(公告)号：JPH11353244A

    公开(公告)日：1999-12-24

    申请号：JP11065099

    申请日：1999-04-19

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  DANNY MARVIN NEIL ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

    IPC: G06F13/00 ,  G06F11/07

    Abstract: PROBLEM TO BE SOLVED: To prevent damage due to a bus error in loading operation or storing operation through the identification of a device which encountered an error before by using forcible illegal data parity or 0-byte enabling. SOLUTION: Device select lines from respective I/O devices 132 and 134 are connected individually to a PCT host bridge 124 and if an error occurs on a PCI(peripheral component interconnect) bus, the device number of the faulty device is recorded in an error register 204. Following loading operation and storing operation are suspended until the error register is reset and until the device number of the object device is checked in the error register. If the object device got out of order before, the completion of the loading/storing operation on the device is stopped by forcing the illegal parity or setting all of byte enabling to zero. The I/O devices activate their device select lines when the illegal parity of 0-byte enabling is forced to answer a load request or store request, but accept no store data.

    4.
    发明专利
    未知

    公开(公告)号：DE69914966D1

    公开(公告)日：2004-04-01

    申请号：DE69914966

    申请日：1999-04-19

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS CRAIG ,  MCLAUGHLIN CHARLES ANDREW ,  NEAL DANNY MARVIN ,  NICHOLSON JAMES OTTO ,  THURBER STEVEN MARK

    IPC: G06F13/00 ,  G06F11/07 ,  G06F11/00

    Abstract: Device selects lines 202n from each I/O device 132 are brought into a PCI host bridge 124 individually so that the device number of a failing device may be logged in an error register 204 when an error is seen on the PCI bus. Until the error register is reset, subsequent load and store operations are delayed until the device number of the subject device may be checked against the error register. If the subject device is a previously failing device, the load/store operation to that device is prevented from completing, either by forcing bad parity or zeroing all byte enables. By forcing bad parity or zero byte enables, the I/O device will respond to the load or store request by activating its device select line, but will not accept store data. Operations to devices which are not logged in the error register are permitted to proceed normally, as are all load store operations when the error register is clear. Normal system operations are thus not impacted, and operations during error recovery are permitted to proceed if no further damage will be caused by such operations.

    6.
    发明专利
    未知

    公开(公告)号：DE69021899D1

    公开(公告)日：1995-10-05

    申请号：DE69021899

    申请日：1990-01-11

    Applicant: IBM

    Inventor： FOGG RICHARD G ,  MATHIS JOSEPH RICHARD ,  NICHOLSON JAMES OTTO

    IPC: G06F13/28

    Abstract: A DMA controller is described which has an attached, dedicated memory. Data objects are stored in this memory and are linked to one another, by pointers. Each data object contains DMA block transfer control parameters. A single block transfer is made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

    7.
    发明专利
    未知

    公开(公告)号：DE69021899T2

    公开(公告)日：1996-04-18

    申请号：DE69021899

    申请日：1990-01-11

    Applicant: IBM

    Inventor： FOGG RICHARD G ,  MATHIS JOSEPH RICHARD ,  NICHOLSON JAMES OTTO

    IPC: G06F13/28

    Abstract: A DMA controller is described which has an attached, dedicated memory. Data objects are stored in this memory and are linked to one another, by pointers. Each data object contains DMA block transfer control parameters. A single block transfer is made up of several separate transfers, with each separate transfer defined by one data object. The single block transfer is defined by linking several data objects into a list. The DMA controller consecutively performs the transfers in a linked list without requiring control by a system central processor.

    9.
    发明专利
    未知

    公开(公告)号：DE68923863D1

    公开(公告)日：1995-09-21

    申请号：DE68923863

    申请日：1989-12-11

    Applicant: IBM

    Inventor： CHANG ALBERT ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  O'QUIN III JOHN CLAUDE ,  O'QUIN II JOHN THOMAS

    IPC: G06F12/08 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24

    Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

    10.
    发明专利
    未知

    公开(公告)号：DE69419680D1

    公开(公告)日：1999-09-02

    申请号：DE69419680

    申请日：1994-09-15

    Applicant: IBM

    Inventor： ARNDT RICHARD LOUIS ,  NICHOLSON JAMES OTTO ,  SILHA EDWARD JOHN ,  THURBER STEVEN MARK ,  YOUNGS AMY MAY

    IPC: G06F15/16 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/177 ,  G06F13/26

    Abstract: An interrupt subsystem within a data processing system is scalable from low-end uniprocessor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queuing of interrupts from many sources, and for queuing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

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