公开(公告)号：DE68923863T2

公开(公告)日：1996-03-28

申请号：DE68923863

申请日：1989-12-11

Applicant: IBM

Inventor： CHANG ALBERT ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  O'QUIN III JOHN CLAUDE ,  O'QUIN II JOHN THOMAS

IPC: G06F12/08 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

公开(公告)号：MX155253A

公开(公告)日：1988-02-10

申请号：MX20112784

申请日：1984-04-25

Applicant: IBM

Inventor： BURNS CHARLES SYDNEY ,  CRABTREE MICHAEL RAY ,  GOURNESU DWIGHT ALLEN ,  HINKEL SCOTT WAYNE ,  LEROM GEORGE ALBERT ,  MAYFIELD MICHAEL JOHN

IPC: G06F13/12 ,  G06F13/28 ,  G03F3/00

公开(公告)号：DE68923863D1

公开(公告)日：1995-09-21

申请号：DE68923863

申请日：1989-12-11

Applicant: IBM

Inventor： CHANG ALBERT ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  O'QUIN III JOHN CLAUDE ,  O'QUIN II JOHN THOMAS

IPC: G06F12/08 ,  G06F12/14 ,  G06F13/12 ,  G06F21/24

Abstract: A cache for use with input/output devices attached to an input/output bus. Requests for access to system memory by an input/output device pass through the cache. Access authority is checked to determine whether an input/output device is authorised to access that particular page. If it is not, access is denied. Each input/output device has access to a portion of the cache, so that activity by one device will not interfere with activity by another.

公开(公告)号：DE3483492D1

公开(公告)日：1990-12-06

申请号：DE3483492

申请日：1984-05-03

Applicant: IBM

Inventor： BURNS CHARLES SIDNEY ,  CRABTREE MICHAEL RAY ,  GOURNEAU DWIGHT ALLEN ,  HINKEL SCOTT WAYNE ,  LEROM GEORGE ALBERT ,  MAYFIELD MICHAEL JOHN

IPC: G06F13/12 ,  G06F13/28

公开(公告)号：DE69021594T2

公开(公告)日：1996-05-02

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.

公开(公告)号：DE69021594D1

公开(公告)日：1995-09-21

申请号：DE69021594

申请日：1990-01-11

Applicant: IBM

Inventor： ARIMILLI RAVI KUMAR ,  DHAWAN SUDHIR ,  LEROM GEORGE ALBERT ,  NICHOLSON JAMES OTTO ,  SIEGEL DAVID WILLIAM

IPC: G06F13/28 ,  G06F13/42

Abstract: A computer system bus is described which includes signal lines for controlling a high speed block data transfer mode between a bus master and a bus slave. When both master and slave devices support such a transfer, a high speed bus clock separate from the normal bus clock is used to transfer data. Devices not involved in the high speed block transfer see only an extended normal data transfer. The master and slave use bus control signals to determine the speed and data width of the high speed transfer. If the slave is unable to transfer the complete block of data at the high speed clock rate, it can signal the master to repeat the transfer of individual data items as necessary.