公开(公告)号：SG105493A1

公开(公告)日：2004-08-27

申请号：SG200102115

申请日：1999-02-15

Applicant: IBM

Inventor： DIANE CATHERINE BOYD ,  STUART M BURNS ,  HUSSEIN IBRAHIM HANAFI ,  YUAN TAUR ,  WILLIAM C WILLE

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

公开(公告)号：SG90231A1

公开(公告)日：2002-07-23

申请号：SG200100583

申请日：2001-02-01

Applicant: IBM

Inventor： DIANE CATHERINE BOYD ,  HUSSEIN IBRAHIM HANAFI ,  MEIKEI LEONG ,  WESLEY CHARLES NATZLE

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/302 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices having a high dielectric constant (k greater than 7) gate insulator, low overlap capacitance (0.35 fF/mum or below) and a channel length (sub-lithographic, e.g., 0.1 mum or less) that is shorter than the lithography-defined gate lengths are provided. The methods include a damascene processing step and a chemical oxide removal (COR) step. The COR step produces a large taper on a pad oxide layer which, when combined with a high-k gate insulator, results in low overlap capacitance, sort channel lengths and better device performance as compared to MOSFET devices that are formed using conventional Complementary Metal Oxide Semiconductor (CMOS) technologies.