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    STACK DEVICE
    1.
    发明专利
    STACK DEVICE 失效

    公开(公告)号：JPH08102530A

    公开(公告)日：1996-04-16

    申请号：JP20311895

    申请日：1995-08-09

    Applicant: IBM

    Inventor： DONARUDO MAKUARUPIN KENII

    IPC: H01L27/04 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/00 ,  H01L27/088 ,  H01L27/092 ,  H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To obtain a stack of subsurface FETs of bulk single-crystal silicon, wherein all the FETs are formed simultaneously and a low-resistance capacitance for the source or darn is provided by providing a constitution such that an electronic device has parts neighboring the horizontal trench in a single- crystal substrate. SOLUTION: This device consists of a bulk single-crystal substrate 120, a horizontal trench 334 embedded in the single-crystal substrate 120 and electronic devices 182 and 186, having parts located in the bulk single-crystal substrate 120. For example, the horizontal trench 334 is formed by using doping-dependent porous silicon etching, and a gate insulating layer 160 and a gate conductor 162 are formed in the inside. Then, a boron-doped glass layer 174 is formed on the sidewall of a vertical trench 172. After n-type dopant ions have been implanted in the bottom part of the vertical trench, annealing is performed, and a p-channel transistor 186 and an n-channel transistor 182 are formed.

    SEMICONDUCTOR MEMORY
    4.
    发明专利
    SEMICONDUCTOR MEMORY 失效

    公开(公告)号：JPH029165A

    公开(公告)日：1990-01-12

    申请号：JP1010289

    申请日：1989-01-20

    Applicant: IBM

    Inventor： DONARUDO MAKUARUPIN KENII

    IPC: G11C11/405 ,  H01L21/8242 ,  H01L27/108

    Abstract: PURPOSE: To form a practical charge amplification memory cell by gating a charge selectively onto a memory node through a write transistor and measuring a current depending on a storage charge passing through a read transistor at the time of reading. CONSTITUTION: A charge representative of a data value is applied onto a memory node 10 coupled through an inner capacity 12 with a high conductivity grounded substrate and through an outer capacity 16 with a word line 14. A write transistor(TR) 20 being gated by a line 22 gates a bit line 18 to the node 10. Furthermore, a charge on the node 10 controls the conductivity of a read TR 24 and an isolation TR 26. During a write operation to the node 10, the line 14 has a high voltage VH while the line 22 has 0V. The voltages VH, 0V are applied to the line 18 and a voltage corresponding to a data appears at the node 10. During a read operation, voltage on the line 14 is lowered from VH down to 0V thus causing oscillation of the voltage at the node 10.

    METHOD OF FORMING MASKING STRUCTURE ON SUBSTRATE
    6.
    发明专利
    METHOD OF FORMING MASKING STRUCTURE ON SUBSTRATE 失效

    公开(公告)号：JPH01124219A

    公开(公告)日：1989-05-17

    申请号：JP19076788

    申请日：1988-08-01

    Applicant: IBM

    Inventor： UIRIAMU JIYOSEFU KOOTO ,  DONARUDO MAKUARUPIN KENII ,  MAIKERU RIN KAABAA ,  MAIKERU ARUBAATO RIICHI ,  JIEFURII AREN ROBINSON ,  ROBAATO UEIN SUIITOSAA

    IPC: H01L21/302 ,  H01L21/027 ,  H01L21/3065 ,  H01L21/311

    Abstract: PURPOSE: To provide spacers on organic mandrels which are formed on a substrate and have vertical side walls without exposing the mandrels to high treating temperatures by adhering organic conformal layers made of a material different from that of the mandrels onto the the mandrels and performing anisotropic etching on the conformal layers. CONSTITUTION: Photoresist mandrels 10 are made of an organic resin material. Since conformal organic layers 20 can be adhered to the mandrels 10 at a room temperature by using such an organic material that can be adhered comformally to the mandrels at a low temperature and etched steps can also be formed at a low temperature, the mandrels 10 are not cured in a heating step. Then spacers 20A are demarcated by performing anisotropic etching on the layers 20 in anisotropic oxygen gas plasma on the side walls of the mandrels 10. After the spacers 20A are demarcated, the mandrels 10 are removed by exposing the mandrels 10 to an etchant which hardly etches the spacers 20A. Therefore, the spacers 20A are left as they are. Then a mask for patterning a conductive layer 14 which lies under etch stop layers 12A and 12B below the spacers 20A is formed by patterning the layers 12A and 12B.

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