公开(公告)号：US3676704A

公开(公告)日：1972-07-11

申请号：US3676704D

申请日：1970-12-29

Applicant: IBM

Inventor： DONOFRIO NICHOLAS M ,  POMERANZ JEHOSHUA N

IPC: G11C11/414 ,  G11C11/416 ,  H03K5/02 ,  H03K5/20

CPC classification number: H03K5/02 ,  G11C11/416

Abstract: This specification describes a sense amplifier/bit driver circuit for a monolithic memory storage cell with a double ended output. The sense amplifier consists of two shunt feedback amplifiers connected differentially across the double ended output of the storage cell. There is a resistive connection between the outputs of the two shunt feedback amplifiers to make each input of the two shunt feedback amplifiers relatively insensitive to large changes at the other input. The bit driver for the circuit contains two current switch circuits for controlling the potential at each end of the double ended output of the storage cell. These current switch circuits are crosscoupled by a transistor which eliminates the need for inverting one of the control pulses to the bit driver.

Abstract translation: 该规范描述了具有双端输出的单片存储器存储单元的读出放大器/位驱动器电路。 读出放大器由两个分流反馈放大器组成，分别跨接在存储单元的双端输出端。 两个并联反馈放大器的输出之间存在电阻连接，以使两个并联反馈放大器的每个输入对另一个输入端的大变化相对不敏感。 电路的位驱动器包含两个电流开关电路，用于控制存储单元的双端输出的每端的电位。 这些电流开关电路通过晶体管交叉耦合，这消除了将控制脉冲之一反转到位驱动器的需要。

公开(公告)号：US3706891A

公开(公告)日：1972-12-19

申请号：US3706891D

申请日：1971-06-17

Applicant: IBM

Inventor： DONOFRIO NICHOLAS M ,  LINTON RICHARD H

IPC: G11C11/403 ,  G11C11/405 ,  H01L27/00 ,  H01L27/108 ,  H03K23/08

CPC classification number: H01L27/108 ,  G11C11/403 ,  G11C11/405 ,  H01L27/00

Abstract: This specification discloses an A.C. stable or stored charge storage cell for use in monolithic memories. The cell includes a capacitor that couples a drive line to a sense line. The capacitance of this capacitor is voltage dependent so that when charged it provides a high capacitance to couple signals on the drive line to the sense line and when discharged it provides a low capacitance to prevent the coupling of signals from the drive line to the sense line.

Abstract translation: 本说明书公开了一种用于单片存储器的稳定或存储的电荷存储单元。 电池包括将驱动线耦合到感测线的电容器。 该电容器的电容取决于电压，因此当充电时，它提供高电容以将驱动线上的信号耦合到感测线路，并且当放电时，它提供低电容以防止信号从驱动线耦合到感测线 。

公开(公告)号：CA992212A

公开(公告)日：1976-06-29

申请号：CA172497

申请日：1973-05-28

Applicant: IBM

Inventor： DESIMONE ROY R ,  DONOFRIO NICHOLAS M ,  LINTON RICHARD H ,  SONODA GEORGE ,  WADE WILLIAM T

IPC: G11C11/412 ,  G11C8/04 ,  G11C8/16 ,  G11C11/402 ,  G11C11/406

Abstract: An electronic data storage which operates as a DC stable storage array, but retains the advantages of an AC stable storage cell circuit. The AC stable storage cells are regenerated at a frequency asynchronous with respect to the storage cycle time. Gating means inhibit the regenerating signals when the system desires access, thereby permitting the storage cells to be accessed for information at any time in a completely random access mode.

公开(公告)号：CA1012654A

公开(公告)日：1977-06-21

申请号：CA174371

申请日：1973-06-19

Applicant: IBM

Inventor： DONOFRIO NICHOLAS M ,  KEMERER DOUGLAS W

IPC: G11C11/41 ,  G11C11/414 ,  G11C11/416

Abstract: The specification describes a sense amplifier/bit driver circuit having an active bit/sense line pull-up circuit. The active pull-up circuit is shown substantially as two transistors connected between the bit driver circuit and the bit/sense lines. A normal write operation is performed by pulling one bit/sense line to a down level (ground) potential and retaining the other bit/sense line at an up level (positive) voltage. Immediately after the write operation, recovery time is required to bring the down level bit/sense line back to the up level for subsequent read/write operations. The pull-up circuit described in the specification is turned on to perform this function and maintained off in order not to interfere with other operations.

公开(公告)号：CA996263A

公开(公告)日：1976-08-31

申请号：CA174375

申请日：1973-06-19

Applicant: IBM

Inventor： BENANTE JOSEPH F ,  DONOFRIO NICHOLAS M ,  LINTON RICHARD H

IPC: G11C11/412 ,  G01R31/27 ,  G01R31/28 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.

公开(公告)号：CA985748A

公开(公告)日：1976-03-16

申请号：CA186190

申请日：1973-11-19

Applicant: IBM

Inventor： DONOFRIO NICHOLAS M ,  KEMERER DOUGLAS W ,  RAYMOND JOHN JR

IPC: H03M7/02 ,  H03K19/096

Abstract: Disclosed is a true complement generator for providing the true and complement values of an input signal as an output, in response to predetermined timing signals. A first portion of the true complement generator is a gated inverter circuit generating a complement output. A second portion of the true complement generator is a gated driver circuit generating a true output. The true and complement phases of the input signal appear at the respective output nodes during the occurrence of a first timing signal, while both output nodes are held to the same level during the occurrence of a second timing signal.