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    A. c. stable storage cell
    2.
    发明授权
    A. c. stable storage cell 失效
    A.稳定存储单元

    公开(公告)号：US3706891A

    公开(公告)日：1972-12-19

    申请号：US3706891D

    申请日：1971-06-17

    Applicant: IBM

    Inventor： DONOFRIO NICHOLAS M ,  LINTON RICHARD H

    IPC: G11C11/403 ,  G11C11/405 ,  H01L27/00 ,  H01L27/108 ,  H03K23/08

    CPC classification number: H01L27/108 ,  G11C11/403 ,  G11C11/405 ,  H01L27/00

    Abstract: This specification discloses an A.C. stable or stored charge storage cell for use in monolithic memories. The cell includes a capacitor that couples a drive line to a sense line. The capacitance of this capacitor is voltage dependent so that when charged it provides a high capacitance to couple signals on the drive line to the sense line and when discharged it provides a low capacitance to prevent the coupling of signals from the drive line to the sense line.

    Abstract translation: 本说明书公开了一种用于单片存储器的稳定或存储的电荷存储单元。 电池包括将驱动线耦合到感测线的电容器。 该电容器的电容取决于电压，因此当充电时，它提供高电容以将驱动线上的信号耦合到感测线路，并且当放电时，它提供低电容以防止信号从驱动线耦合到感测线 。

    Monolithic capacitor structure
    3.
    发明授权
    Monolithic capacitor structure 失效
    单片电容器结构

    公开(公告)号：US3704384A

    公开(公告)日：1972-11-28

    申请号：US3704384D

    申请日：1971-03-30

    Applicant: IBM

    Inventor： DESIMONE ROY R ,  LINTON RICHARD H

    IPC: H01L21/00 ,  H01L21/822 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/00 ,  H01L29/78 ,  H01L11/14

    CPC classification number: H01L21/00 ,  H01L27/04 ,  H01L27/105 ,  H01L27/108 ,  H01L29/00

    Abstract: This specification discloses a polarized capacitor for use in monolithic structures, particularly those using field effect transistors. One plate of this capacitor is a metal layer overlying and insulated from a semiconductor body which has a diffusion in it adjacent to the overlying metal layer. The boundaries of this diffusion form a rectifying junction with the rest of the semiconductor body. When a voltage is applied between the metal layer and the diffusion an electric field is formed under the layer and adjacent to the diffusion so as to create an inversion layer which forms with the diffusion the second plate of the capacitor.

    Abstract translation: 本说明书公开了一种用于单片结构的极化电容器，特别是使用场效应晶体管的电容器。 该电容器的一个板是与半导体本体重叠并绝缘的金属层，半导体本体在其邻近金属层附近具有扩散。 该扩散的边界与半导体本体的其余部分形成整流结。 当在金属层和扩散层之间施加电压时，在该层下方并且与扩散相邻形成电场，从而产生与电容器的第二板扩散形成的反型层。

    Storage cell with variable power level
    4.
    发明授权
    Storage cell with variable power level 失效
    具有可变功率级的存储单元

    公开(公告)号：US3588846A

    公开(公告)日：1971-06-28

    申请号：US3588846D

    申请日：1968-12-05

    Applicant: IBM

    Inventor： LINTON RICHARD H ,  SONODA GEORGE Y

    IPC: G11C11/402 ,  G11C11/412 ,  G11C11/40 ,  H03K3/286

    CPC classification number: G11C11/4023 ,  G11C11/412

    Abstract: THIS SPECIFICATION DESCRIBES A SEMICONDUCTOR STORAGE CELL FOR USE IN MONOLITHIC MEMORIES. THE STORAGE CELL HAS TWO CROSSCOUPLED FET''S WHICH FUNCTION AS THE STORAGE ELEMENTS OF THE CELL. THE CROSSCOUPLED FET''S ARE ADDRESSED POWERED THROUGH INPUT-OUTPUT FET''S WHEN THE CELL IS INTERROGATED FOR READING. WHEN THE CELL IS NOT BEING SO INTERROGATED, THE CROSSCOUPLED FET''S ARE SUPPLIED POWER FROM A SOURCE WHICH IS CONNECTED TO EACH OF THE CROSSCOUPLED FET''S BY A SEPARATE LOAD FET. THE GATES OF THOSE LOAD FET''S ARE BIASED SO THE LOAD FET''S SUPPLY CHARGE TO THE CROSSCOUPLED FET''S WHILE THE STORAGE CELL IS NOT BEING INTERROGATED BUT DRAW CHARGE FROM THE CROSSCOUPLED FET''S WHEN THE CROSSCOUPLED FET''S ARE ADDRESSED FOR READING. BY BIASING THE LOAD FET''S IN THIS

    MANNER, THE POTENTIAL ON THE DRAIN CAN BE REDUCED SO AS TO REDUCE THE OVERALL POWER DISSIPATION OF THE STORAGE CELL.

    METHOD AND APPARATUS FOR DETERMINING THE ELECTRICAL CHARACTERISTICS OF A MEMORY CELL NG FIELD EFFECT TRANSISTORS
    6.
    发明专利
    METHOD AND APPARATUS FOR DETERMINING THE ELECTRICAL CHARACTERISTICS OF A MEMORY CELL NG FIELD EFFECT TRANSISTORS 未知

    公开(公告)号：CA996263A

    公开(公告)日：1976-08-31

    申请号：CA174375

    申请日：1973-06-19

    Applicant: IBM

    Inventor： BENANTE JOSEPH F ,  DONOFRIO NICHOLAS M ,  LINTON RICHARD H

    IPC: G11C11/412 ,  G01R31/27 ,  G01R31/28 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56

    Abstract: The electrical characteristics of a field effect transistor (FET) of a memory cell connected to a ZERO bit line and of an FET of the memory cell connected to a ONE bit line are determined through applying a substantially constant voltage to one of the ZERO and ONE bit lines while changing the voltage condition on the other of the bit lines. In one embodiment, the FET is a load device of the memory cell and has its source electrode connected to one of the bit lines and also to the drain electrode of another FET, which has its gate electrode connected to the other of the bit lines and functions as an active device of the cell. A substantially constant voltage is applied to the gate electrode through one of the bit lines to inactivate the FET which has its drain electrode connected to the source electrode of the FET having its electrical characteristics determined. The other of the bit lines is discharged for a predetermined period of time and then allowed to charge for another predetermined period of time. The measurement of this charged voltage will indicate whether the FET, which is the load device, is connected to the bit line and has the desired gain and whether the leakage current through the bit line is too high. In the other embodiment, a substantially constant voltage is applied to an FET which is the active device and has its drain electrode connected to one of the bit lines to have a substantially constant voltage applied thereto while its gate electrode is connected to the other of the bit lines to have two different voltages applied thereto. The difference in current flow through the active FET having the two different voltages applied to its gate electrode is employed to determine the threshold voltage of the FET.

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