公开(公告)号：US3576973A

公开(公告)日：1971-05-04

申请号：US3576973D

申请日：1969-04-30

Applicant: IBM

Inventor： DRAPER WILBURN D

IPC: G06F7/38 ,  G06F7/508 ,  H03K23/66 ,  G06M3/14 ,  H03K21/06

CPC classification number: H03K23/665

Abstract: A versatile binary register which has control means for selectively setting the register to the one''s and two''s complements in response to first and second control signals, respectively. In addition, alternate application of the first and second control signals causes the register to function as a counter which operates in the forward mode if the first and second control signals are applied in a given sequence and/or operates in the reverse mode if the signals are applied in an opposite sequence.

公开(公告)号：CA1119275A

公开(公告)日：1982-03-02

申请号：CA325548

申请日：1979-04-11

Applicant: IBM

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F15/16

Abstract: SELECT SYSTEM FOR PRIORITY INTERFACE CIRCUITRY Selection of adapters belonging to a communications controller. The adapter of rank "i" registers in APi the highest priority level from amongst the services required of it by the elements it services. A comparison is made in an asynchronous manner between the level in APi and the priority levels of adapters of rank i+l through n. A SER SELECT line propagates down to up line the result which is obtained from said comparison and is utilized to set one of the latches S and to reset the other ones. The selection of the adapter to be serviced it limited to locating the latch S which is set. Data communications.

公开(公告)号：FR2428284A1

公开(公告)日：1980-01-04

申请号：FR7817709

申请日：1978-06-07

Applicant: IBM FRANCE

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/374

Abstract: A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.

公开(公告)号：CA1172382A

公开(公告)日：1984-08-07

申请号：CA406380

申请日：1982-06-30

Applicant: IBM

Inventor： DRAPER WILBURN D ,  LAAKSO MELVIN T

IPC: G06F11/00 ,  G06F11/30 ,  G06F13/00 ,  G06F13/12 ,  G06F3/04

Abstract: MULTI SUB-CHANNEL ADAPTER WITH SINGLE STATUS/ADDRESS REGISTER An improved adapter for a programmed control unit arranged to be operated in facilitating I/O operations between one or more I/O devices and a CPU through a channel. The improved adapter includes a local store which store has a hardware register dedicated to store device status and the associated address in connection with test I/O commands. Thus, in accordance with the method of the invention on receiving a status request the improved adapter responds immediately with a response indicating that the information is not immediately available, for example, a busy response. The improved adapter initiates an interrupt to the program control unit to obtain the requested status information, which is then stored in dedicated hardware registers of the local store. On the next subsequent test I/O command to the same address, the improved adapter responds with the status as read from the dedicated hard are register. In another aspect the invention provides an improved adapter which includes communication path means, for example hardware registers, passing data to and from the channel and attached devices, and a further hardware register of sufficient capacity to store a status word and an associated address. the adapter also includes a bus for transferring a status word and associated address from the attached control unit in response to a channel received command to the further hardware register and, control circuitry which is responsive to a subsequent status request and command associated with the associated address, for placing the status word from the further hardware register on the channel. The adapter sup ports both host or control unit initiated I/O status transfers, i.e. both synchronous and asynchronous.

公开(公告)号：DE2966775D1

公开(公告)日：1984-04-19

申请号：DE2966775

申请日：1979-04-23

Applicant: IBM

Inventor： DALBOUSSIERE GERARD ,  DRAPER WILBURN D

IPC: G06F9/46 ,  G06F13/00 ,  G06F13/374 ,  H04Q3/54 ,  G06F3/04

Abstract: A dynamic preselect interrupt priority circuit in which a plurality of adapters dynamically readjust priority until selected whereupon adjustment stops and the adapter having the highest interrupt and position priority is selected.