中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

4 records (took 0.018 seconds)

    MULTI SUB-CHANNEL ADAPTER WITH SINGLE STATUS/ADDRESS REGISTER
    2.
    发明专利
    MULTI SUB-CHANNEL ADAPTER WITH SINGLE STATUS/ADDRESS REGISTER 未知

    公开(公告)号：CA1172382A

    公开(公告)日：1984-08-07

    申请号：CA406380

    申请日：1982-06-30

    Applicant: IBM

    Inventor： DRAPER WILBURN D ,  LAAKSO MELVIN T

    IPC: G06F11/00 ,  G06F11/30 ,  G06F13/00 ,  G06F13/12 ,  G06F3/04

    Abstract: MULTI SUB-CHANNEL ADAPTER WITH SINGLE STATUS/ADDRESS REGISTER An improved adapter for a programmed control unit arranged to be operated in facilitating I/O operations between one or more I/O devices and a CPU through a channel. The improved adapter includes a local store which store has a hardware register dedicated to store device status and the associated address in connection with test I/O commands. Thus, in accordance with the method of the invention on receiving a status request the improved adapter responds immediately with a response indicating that the information is not immediately available, for example, a busy response. The improved adapter initiates an interrupt to the program control unit to obtain the requested status information, which is then stored in dedicated hardware registers of the local store. On the next subsequent test I/O command to the same address, the improved adapter responds with the status as read from the dedicated hard are register. In another aspect the invention provides an improved adapter which includes communication path means, for example hardware registers, passing data to and from the channel and attached devices, and a further hardware register of sufficient capacity to store a status word and an associated address. the adapter also includes a bus for transferring a status word and associated address from the attached control unit in response to a channel received command to the further hardware register and, control circuitry which is responsive to a subsequent status request and command associated with the associated address, for placing the status word from the further hardware register on the channel. The adapter sup ports both host or control unit initiated I/O status transfers, i.e. both synchronous and asynchronous.

    RECEIVE/BYPASS CIRCUIT FOR SUBSYSTEMS IN POLLING SYSTEM
    4.
    发明专利
    RECEIVE/BYPASS CIRCUIT FOR SUBSYSTEMS IN POLLING SYSTEM 未知

    公开(公告)号：CA1124813A

    公开(公告)日：1982-06-01

    申请号：CA332646

    申请日：1979-07-27

    Applicant: IBM

    Inventor： CONNER DAVID E ,  HOFFMAN CHARLES R ,  LAAKSO MELVIN T

    IPC: G06F13/00 ,  G06F11/20 ,  H04L12/423 ,  H04L12/437 ,  H04Q1/20

    Abstract: RECEIVE/BYPASS CIRCUIT FOR SUBSYSTEMS IN POLLING SYSTEM A polling system includes a central processor and a plurality of subsystems connected in a loop to the central processor. A receive/bypass circuit in each subsystem includes a depletion mode field effect transistor having its drain and source electrodes connected in series in a bypass line at the subsystem. A control circuit is connected to a polling signal input line at each subsystem. When the subsystem has power, the control circuit routes the polling signal to a terminal device in the subsystem while establishing a conduction-inhibiting voltage at the gate electrode of the field effect transistor. When the subsystem is unpowered or out of service, a switching transistor in the control circuit isolates the terminal device from the polling signal input line. The polling signal bypasses an unpowered subsystem through the unbiased field effect transistor in the bypass line. RA9-77-009

Patent Agency Ranking