公开(公告)号：JPH10242389A

公开(公告)日：1998-09-11

申请号：JP2700998

申请日：1998-02-09

Applicant: IBM

Inventor： EDWARD J NOWAKU ,  TEIEN SHAOUEI ,  MIN H TON

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To provide a noise separation burial resistor that satisfies the requirements of a low-noise analog design requiring a properly controlled ohm resistor. SOLUTION: An electric field shielding is provided between a buried resistor and a substrate to separate the buried resistor from the noise of a substrate by a standard buried resistor layout and a mask sequence with two exceptions. First, the buried resistor is not simply arranged at the region of a P well 13 but arranged at the region of an N well 4. Second, to electrically separate the buried resistor from the N well 14, a boron impregnant is added via the buried resistor mask and the P well 13 is formed inside the N well 14, thus electrically connecting the N well 14 to the noiseless ground. The P well 13 inside the N well 14 is left in floating state.

公开(公告)号：JP2002314094A

公开(公告)日：2002-10-25

申请号：JP2002052160

申请日：2002-02-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  LASKY JEROME B ,  EDWARD J NOWACK ,  RANKIN JED H ,  MIN H TON

IPC: H01L29/43 ,  H01L21/336 ,  H01L21/74 ,  H01L21/762 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/08 ,  H01L27/11 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and a structure for avoiding a floating body effect in an SOI structure. SOLUTION: A semiconductor device includes SOI FETs which include silicon bodies on an insulating layer on a conductive substrate. Gate dielectrics and gates are formed on the surfaces of the silicon bodies, and sources and drains are formed on two sides of the gates. Buried body contacts to substrate conductors are formed under the third side of the gate. The buried body contacts do not extend to the upper face of the silicon bodies. The buried body contacts are separated from the gates by second dielectrics whose thicknesses are generally larger than the thicknesses of the first gate dielectrics. The buried body contacts are plugs made of conductive materials, and the second dielectrics cover the body contacts under the gates. The FETs can be used in a SRAM circuit or any other type of circuit having the silicon on insulator(SOI) structure.

公开(公告)号：JP2000150784A

公开(公告)日：2000-05-30

申请号：JP33913499

申请日：1999-11-30

Applicant: IBM

Inventor： EDWARD J NOWAKU ,  TIAN XIAOWEI ,  MIN H TON

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To enable a noise-insulated buried resistor to meet the requirement of a low-noise analog design requiring a well controlled ohmic resistor. SOLUTION: In order to insulate a buried resistor from the noise of a substrate, an electric field shield composed of an N-well 14 is formed between the buried resistor and substrate. The buried resistor 11 is formed in a P-well 13 formed in the N-well 14. A shallow trench separating area 12 is extended over the wells 13 and 14 and has an opening forming to expose a prescribed surface area in the well 13, and the resistor area 11 is formed in the area of the well 13 demarcated by the opening.

公开(公告)号：JPH11317499A

公开(公告)日：1999-11-16

申请号：JP890299

申请日：1999-01-18

Applicant: IBM

Inventor： EDWARD J NOWACK ,  SHAO WEI TAN ,  MIN H TON

IPC: H01L27/04 ,  H01L21/329 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108 ,  H01L29/94

Abstract: PROBLEM TO BE SOLVED: To achieve a semiconductor with an improved embedded resistor and an embedder capacitor by arranging a polysilicon gate on the region of a resistance element and arranging a separation layer between the polysilicon gate and the resistance element. SOLUTION: A semiconductor device includes a substrate, a characteristic polysilicon gate 58, a resistance element, and a separation layer. The polysilicon gate 58 is arranged on the region of the resistance element, and the separation layer is arranged between the polysilicon gate 58 and the resistance element. Also, an embedded resistor 52 is an N-type dope and is provided with a P well 64. The diffusion resistor 52 is an N-type doping. Input 54 and output 56 are in electrical contact. An N-type source doping/drain doping 60 is located at the lower side of the region of the input 54 and the output 56. Since the P well in placed away from the lower portion of the diffusion resistor 52, parasitic junction capacitance is low. Therefore, the execution is simple, so that the change costs of a device does not become too high.