公开(公告)号：JP2000150784A

公开(公告)日：2000-05-30

申请号：JP33913499

申请日：1999-11-30

Applicant: IBM

Inventor： EDWARD J NOWAKU ,  TIAN XIAOWEI ,  MIN H TON

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/8605

Abstract: PROBLEM TO BE SOLVED: To enable a noise-insulated buried resistor to meet the requirement of a low-noise analog design requiring a well controlled ohmic resistor. SOLUTION: In order to insulate a buried resistor from the noise of a substrate, an electric field shield composed of an N-well 14 is formed between the buried resistor and substrate. The buried resistor 11 is formed in a P-well 13 formed in the N-well 14. A shallow trench separating area 12 is extended over the wells 13 and 14 and has an opening forming to expose a prescribed surface area in the well 13, and the resistor area 11 is formed in the area of the well 13 demarcated by the opening.

公开(公告)号：JPH10261766A

公开(公告)日：1998-09-29

申请号：JP3990998

申请日：1998-02-23

Applicant: IBM

Inventor： BROWN JEFFREY S ,  GAUTHIER ROBERT J JR ,  TIAN XIAOWEI

IPC: H01L21/76 ,  H01L21/322 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: PROBLEM TO BE SOLVED: To improve a CMOS device in latch-up resistance by a method wherein an injected part formed under a shallow trench isolation between an N-channel device and a P-channel device is used. SOLUTION: An N-channel device is isolated from a P-channel device by the use of a shallow trench isolation STI 102. The shallow trench isolation STI 102 is formed by removing a part of a wafer which is not covered with a masking layer 104 through a reactive ion etching method. In a following process, an N-channel device and a P-channel device are formed on a wafer part 100. Then, element is injected to form an injected part 106 below the STI 102. It is preferable that the element of the injected part 106 is selected so as to make an N well or a P well minimum in counter doping. Therefore, it is preferable that the element contains large and heavy element.

公开(公告)号：SG60207A1

公开(公告)日：1999-02-22

申请号：SG1998000433

申请日：1998-02-26

Applicant: IBM

Inventor： BROWN JEFFERY S ,  GAUTHIER ROBERT J JR ,  TIAN XIAOWEI

IPC: H01L21/76 ,  H01L21/322 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L21/336

Abstract: The preferred embodiment of the present invention overcomes the imitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by reducing the mobility of carriers between the devices. The preferred embodiment uses an implant formed beneath trench isolation between n-channel and p-channel devices. This implant preferably comprises relatively large/heavy elements implanted into the wafer beneath the trench isolation. The implant elements reduce the mobility of the charge carriers. This increases the latch-up holding voltage and thus reduces the likelihood of latch-up. The implants can be formed without the need for additional photolithography masks.

公开(公告)号：MY120978A

公开(公告)日：2005-12-30

申请号：MYPI9800730

申请日：1998-02-20

Applicant: IBM

Inventor： BROWN JEFFERY S ,  GAUTHIER ROBERT J JR ,  TIAN XIAOWEI

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/322 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

Abstract: THE PREFERRED EMBODIMENT OF THE PRESENT INVENTION OVERCOMES THE LIMITATIONS OF THE PRIOR ART AND PROVIDES A DEVICE AND METHOD TO INCREASE THE LATCH-UP IMMUNITY OF CMOS DEVICES BY REDUCING THE MOBILITY OF CARRIERS BETWEEN THE DEVICES. THE PREFERRED EMBODIMENT USES AN IMPANT (106) FORMED BENEATH TRENCH ISOLATION (102) BETWEEN N-CHANNEL AND P-CHANNEL DEVICES. THIS IMPLANT PREFERABLY COMPRISES RELATIVELY LARGE/HEAVY ELEMETS IMPLANTED INTO THE WAFER(100) BENEATH THE TRENCH ISOLATION. THE IMPLANT ELEMENTS REDUCE THE MOBILITY OF THE CHARGE CARRIERS. THIS INCREASES THE LATCH-UP HOLDING VOLTAGE AND THUS REDUCES THE LIKELIHOOD OF LATCH-UP. THE IMPLANTS CAN BE FORMED WITHOUT THE NEED FOR ADDITIONAL PHOTOLITHOGRAPHY MASKS.FIGURE 4