METHOD AND SYSTEM FOR CORRECTING LONG BURSTS OF CONSECUTIVE ERRORS

    公开(公告)号:CA1309495C

    公开(公告)日:1992-10-27

    申请号:CA603836

    申请日:1989-06-23

    Applicant: IBM

    Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining. SA9-88-041

    SEQUENTIAL ENCODING AND DECODING OF VARIABLE WORD LENGTH FIXED RATE DATA CODES

    公开(公告)号:CA1081849A

    公开(公告)日:1980-07-15

    申请号:CA332286

    申请日:1979-07-20

    Applicant: IBM

    Abstract: SEQUENTIAL ENCODING AND DECODING OF VARIABLE WORD LENGTH, FIXED RATE DATA CODES A method of encoding or decoding data in a code of variable length words and fixed rate comprises the steps of (1) initially entering a constant number (k) of input bits into a shift register; (2) entering a constant number (m) of input bits into the shift register; (3) encoding or decoding a constant number (n) of bits in response to the contents of the shift register; and (4) repeating steps (2) and (3) until the input bits are exhausted. To complete the encoding or decoding, steps (2) and (3) are further repeated with dummy input bits until (k) dummy bits have been entered into the shift register. The encoding or decoding of (n) bits may be affected by auxiliary state variables which account for the position in the shift register of the boundary between words.

    SEQUENTIAL ENCODING AND DECODING OF VARIABLE WORD LENGTH FIXED RATE DATA CODES

    公开(公告)号:CA1075817A

    公开(公告)日:1980-04-15

    申请号:CA223702

    申请日:1975-04-02

    Applicant: IBM

    Abstract: SEQUENTIAL ENCODING AND DECODING OF VARIABLE WORD LENGTH, FIXED RATE DATA CODES A method of encoding or decoding data in a code of variable length words and fixed rate comprises the steps of (1) initially entering a constant number (k) of input bits into a shift register; (2) entering a constant number (m) of input bits into the shift register; (3) encoding or decoding a constant number (n) of bits in response to the contents of the shift register; and (4) repeating steps (2) and (3) until the input bits are exhausted. To complete the encoding or decoding, steps (2) and (3) are further repeated with dummy input bits until (k) dummy bits have been entered into the shift register. The encoding or decoding of (n) bits may be affected by auxiliary state variables which account for the position in the shift register of the boundary between words.

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