公开(公告)号：WO2006117394A2

公开(公告)日：2006-11-09

申请号：PCT/EP2006062046

申请日：2006-05-04

Applicant: IBM ,  IBM UK ,  ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

Inventor： ARMSTRONG WILLIAM JOSEPH ,  ARNDT RICHARD LOUIS ,  CORRIGAN MICHAEL JOSEPH ,  ENGEBRETSEN DAVID ROBERT ,  MARCHINI TIMOTHY RICHARD ,  NAYAR NARESH

IPC: G06F12/10

CPC classification number: G06F3/065 ,  G06F3/0611 ,  G06F3/0673 ,  G06F12/109

Abstract: Managing computer memory in a computer with dynamic logical partitioning that operates transparently with respect to operating systems in logical partitions. Exemplary methods, systems, and products are described for managing computer memory in a computer with dynamic logical partitioning that include copying by a hypervisor, from page frames in one logical memory block ("LMB") of a logical partition ("LPAR") to page frames outside the LMB, contents of page frames having page frame numbers in a page table for an operating system in the LPAR. Embodiments typically include storing new page frame numbers in the page table, including storing by the hypervisor, for each page frame whose contents are copied, a new page frame number that identifies the page frame to which contents are copied. In typical embodiments, copying contents of page frames and storing new page frame numbers are carried out transparently with respect to the operating system.

Abstract translation: 在具有相对于逻辑分区中的操作系统透明运行的动态逻辑分区的计算机中管理计算机内存。 描述了用于在具有动态逻辑划分的计算机中管理计算机存储器的示例性方法，系统和产品，其包括由管理程序从逻辑分区（“LPAR”）的一个逻辑存储块（“LMB”）中的页面帧到 在LMB之外的页框，在LPAR中的操作系统的页表中具有页框号的页框内容。 实施例通常包括在页面表中存储新的页面帧号码，包括由管理程序存储针对其内容被复制的每个页面帧的新的页面帧号码，其标识内容被复制到的页面帧。 在典型的实施例中，相对于操作系统透明地执行复印页面的内容和存储新的页面帧号码。

公开(公告)号：EP0767424A3

公开(公告)日：1998-10-21

申请号：EP96306526

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F9/3013 ,  G06F9/35 ,  G06F9/383

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

公开(公告)号：JP2003030167A

公开(公告)日：2003-01-31

申请号：JP2002124159

申请日：2002-04-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： BEUKEMA BRUCE LEROY ,  BOOTH RICHARD CHARLES ,  ENGEBRETSEN DAVID ROBERT ,  SAND THOMAS REMBERT ,  VALK KENNETH MICHAEL

IPC: G06F15/177 ,  G06F9/46 ,  G06F9/52 ,  G06F15/16

CPC classification number: G06F9/52

Abstract: PROBLEM TO BE SOLVED: To provide a clustered computer system, bridge device and method including support for an atomic ownership change operation of an input/output bridge device. SOLUTION: A lock indicator is associated with a bridge device, and is used to indicate a 'locked' or 'unlocked' status of the bridge device. Whenever the lock indicator indicates that the bridge device is unlocked, an atomic operation such as a read request to a lock indicator resister is utilized to both set the indicator to indicate a lock status to the bridge device, and to associate the bridge device with a source node that initiated the atomic operation. Write access to one or more configuration parameter registers is controlled such that only the node that is associated with the bridge device is permitted to update such configuration parameter registers.

Abstract translation: 要解决的问题：提供一种集群计算机系统，桥接设备和方法，包括支持输入/输出桥接设备的原子所有权变更操作。 解决方案：锁定指示器与桥接设备相关联，用于指示桥接设备的“锁定”或“解锁”状态。 每当锁定指示器指示桥接设备被解锁时，利用诸如对锁定指示器寄存器的读取请求的原子操作来将指示器设置为指示桥接设备的锁定状态，并且将桥接设备与 源节点启动原子操作。 控制对一个或多个配置参数寄存器的写入访问，使得仅允许与桥接器件相关联的节点来更新这样的配置参数寄存器。

公开(公告)号：DE69620702T2

公开(公告)日：2003-04-03

申请号：DE69620702

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

公开(公告)号：DE112011102415B4

公开(公告)日：2018-09-13

申请号：DE112011102415

申请日：2011-07-14

Applicant: IBM

Inventor： WALK BRUCE MARSHALL ,  CORRIGAN MICHAEL ,  ENGEBRETSEN DAVID ROBERT

IPC: G06F13/36 ,  G06F15/173 ,  H04L1/18 ,  H04L12/433 ,  H04L45/58

Abstract: Vorrichtung, aufweisend:eine Vielzahl von Server-Computern;eine Vielzahl von verteilten Brückenelementen, die mit der Vielzahl von Server-Computern Daten austauschen, wobei jedes verteilte Brückenelement so konfiguriert ist, dass es als Reaktion auf ein Empfangen eines Datenrahmens, der eine Registerzugriffsanforderung enthält, auf ein Register zugreift;einen Hauptregisterring, der mit der Vielzahl von Brückenelementen verbunden ist, wobei der Hauptregisterring ein Token-Protokoll für das Zugreifen auf das Register enthält; undeine Steuerbrücke, die so konfiguriert ist, dass sie die Vielzahl von verteilten Brückenelementen steuert und den Datenrahmen erzeugt und zu mindestens einer der Vielzahl von Brückenelementen überträgt,wobei der Datenrahmen eine Folgenummer enthält, welche zu der Registerzugriffsanforderung zugeordnet ist, und wobei die Steuerbrücke so konfiguriert ist, dass die Folgenummer zur Bestätigung einer Übermittlung oder zum Erkennen eines Datenrahmenverlusts verwendet wird undwobei als Reaktion auf einen Datenrahmenverlust Korrekturmaßnahmen initiiert werden und der entsprechende Datenrahmen mit der Registerzugriffsanforderung erneut gesendet wird.

公开(公告)号：DE112011102415T5

公开(公告)日：2013-06-06

申请号：DE112011102415

申请日：2011-07-14

Applicant: IBM

Inventor： WALK BRUCE MARSHALL ,  CORRIGAN MICHAEL ,  ENGEBRETSEN DAVID ROBERT

IPC: G06F13/40 ,  H04L12/433 ,  H04L45/58

Abstract: Systeme und Verfahren zum Durchführen eines Registerzugriffs werden beschrieben. Ein bestimmtes Verfahren weist ein Empfangen eines Datenrahmens bei einem Brückenelement aus einer Vielzahl von Brückenelementen auf, die mit einer Vielzahl von Server-Computern Daten austauschen. Der Datenrahmen kann eine Registerzugriffsanforderung enthalten und von einer Steuerbrücke weitergeleitet werden, die mit der Vielzahl von Brückenelementen Daten austauscht. Als Reaktion auf das Empfangen des Datenrahmens kann auf ein Register zugegriffen und die Ausführung der Registerzugriffsanforderung initialisiert werden.

公开(公告)号：DE69620702D1

公开(公告)日：2002-05-23

申请号：DE69620702

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.