中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.016 seconds)

    Processor with compiler-allocated, variable length intermediate storage
    1.
    发明公开
    Processor with compiler-allocated, variable length intermediate storage 失效
    处理器由编译器分配高速缓存可变长度

    公开(公告)号：EP0767424A3

    公开(公告)日：1998-10-21

    申请号：EP96306526

    申请日：1996-09-09

    Applicant: IBM

    Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

    IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

    CPC classification number: G06F9/3013 ,  G06F9/35 ,  G06F9/383

    Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

    2.
    发明专利
    未知

    公开(公告)号：DE69620702T2

    公开(公告)日：2003-04-03

    申请号：DE69620702

    申请日：1996-09-09

    Applicant: IBM

    Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

    IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

    Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

    5.
    发明专利
    未知

    公开(公告)号：BR8903161A

    公开(公告)日：1990-02-06

    申请号：BR8903161

    申请日：1989-06-28

    Applicant: IBM

    Inventor： GALLAGHER PATRICK WAYNE ,  GREGOR STEVEN LEE ,  REEVE STEPHEN MICHAEL

    IPC: G06F12/08 ,  G06F13/14

    Abstract: Multi level cache storage system for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in the level two cache is updated, corresponding data in level one caches is invalidated until it is updated.

    6.
    发明专利
    未知

    公开(公告)号：DE69620702D1

    公开(公告)日：2002-05-23

    申请号：DE69620702

    申请日：1996-09-09

    Applicant: IBM

    Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

    IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

    Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

    MULTIWAY ASSOCIATIVE EXTERNAL MICROPROCESSOR CACHE
    7.
    发明专利
    MULTIWAY ASSOCIATIVE EXTERNAL MICROPROCESSOR CACHE 未知

    公开(公告)号：CA2240619A1

    公开(公告)日：1998-12-12

    申请号：CA2240619

    申请日：1998-06-11

    Applicant: IBM

    Inventor： JEREMIAH THOMAS LEO ,  GREGOR STEVEN LEE

    IPC: G06F12/08 ,  G06F13/20

    Abstract: A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop b usy time, and for responding to MRU misses and cache misses. A multiway cache includes a single ar ray partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding da ta is accessed from alternate slots while searching said directory, thereby reducing the latency pen alty for cache access.

Patent Agency Ranking