公开(公告)号：JPH02268515A

公开(公告)日：1990-11-02

申请号：JP5391390

申请日：1990-03-07

Applicant: IBM

Inventor： JIERAARU BUDON ,  PIEERU MORIE ,  JIYAN POORU NIITSU ,  ENGU ONGU ,  PASUKARU TANOFU ,  FURANKU WARAARU

IPC: H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

Abstract: PURPOSE: To attain a maximum swing providing a desired CMOS compatibility to a BICMOS logic circuit by connecting an interface circuit means to an output terminal of the BICMOS logic circuit. CONSTITUTION: An interface circuit C1 executing the same logic function of a BICMOS circuit 11 such as an AND function is connected to a terminal 15 of the circuit 11. The interface circuit C1 includes 4 FETs, 2 NFETs N6, N7 and 2 PFETs, P3, P4. The interface circuit C1 operated even singly provide desired heavy load drive capability to the BICMOS circuit 11 and gives a maximum voltage swing required for the CMOS/BICMOS compatibility. Thus, the improved BICMOS circuit is formed by the combination of the circuit 11 and the interface circuit C1 with an excellent characteristic and the compatibility with the CMOS is attained.

公开(公告)号：JPH02303066A

公开(公告)日：1990-12-17

申请号：JP9781690

申请日：1990-04-16

Applicant: IBM

Inventor： MARUTAN BONOO ,  ERITSUKU GUUZE ,  ROBEERU HOONINGU ,  ENGU ONGU ,  JIYAN MARUKU PIKIINO

IPC: H01L21/82 ,  H01L27/118

Abstract: PURPOSE: To easily and efficiently realize all the libraries of a logic circuit in a gate array by providing core cells, each of which contains a plurality of FETs having different optimized sizes. CONSTITUTION: Continuous stripes of core cells arranged adjacently and repeatedly in a row direction are provided. In only core cells CELL 1 and CELL 2 are shown in the figure. The core cells are formed in a functional gate area 21, demarcated along the row direction and having a height H. For example, the cell CELL 1 contains four FETs formed of source/drain diffusion regions, namely, the cell CELL 1 contains one small NFET N1.1 and one large PFET P2.1 having widths WN1, WN2, WP1, and WP2 respectively having reference numbers 22, 23,..., 25. By providing such core cells containing a plurality of FETs having different optimized sizes, a gate-array type master-sliced IC which is realized on a logic semiconductor chip is obtained.