中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.019 seconds)

    BI-CMOS LOGIC CIRCUIT
    1.
    发明专利
    BI-CMOS LOGIC CIRCUIT 失效

    公开(公告)号：JPH02268515A

    公开(公告)日：1990-11-02

    申请号：JP5391390

    申请日：1990-03-07

    Applicant: IBM

    Inventor： JIERAARU BUDON ,  PIEERU MORIE ,  JIYAN POORU NIITSU ,  ENGU ONGU ,  PASUKARU TANOFU ,  FURANKU WARAARU

    IPC: H03K17/567 ,  H03K5/007 ,  H03K19/013 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/0944

    Abstract: PURPOSE: To attain a maximum swing providing a desired CMOS compatibility to a BICMOS logic circuit by connecting an interface circuit means to an output terminal of the BICMOS logic circuit. CONSTITUTION: An interface circuit C1 executing the same logic function of a BICMOS circuit 11 such as an AND function is connected to a terminal 15 of the circuit 11. The interface circuit C1 includes 4 FETs, 2 NFETs N6, N7 and 2 PFETs, P3, P4. The interface circuit C1 operated even singly provide desired heavy load drive capability to the BICMOS circuit 11 and gives a maximum voltage swing required for the CMOS/BICMOS compatibility. Thus, the improved BICMOS circuit is formed by the combination of the circuit 11 and the interface circuit C1 with an excellent characteristic and the compatibility with the CMOS is attained.

    VERTICAL TYPE INSULATED COLLECTOR P-N-P TRANSISTOR STRUCTURE
    3.
    发明专利
    VERTICAL TYPE INSULATED COLLECTOR P-N-P TRANSISTOR STRUCTURE 失效

    公开(公告)号：JPH0541487A

    公开(公告)日：1993-02-19

    申请号：JP4372191

    申请日：1991-03-08

    Applicant: IBM

    Inventor： DOMINIKU BONUU ,  MIRIAMU KOMUBE ,  ANSONII JIEI DARII ,  PIEERU MORIE ,  SEIKI OGURA ,  PASUKARU TANOFU

    IPC: H01L27/06 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732 ,  H01L29/74

    Abstract: PURPOSE: To provide a high-performance longitudinal-type insulating collector PNP transistor structure. CONSTITUTION: This structure includes a P -region 45 for emitter, N-region 44 for base and P-well region 46 for collector, the P-well region 46 is surrounded with an N-type pocket composed of an N -embedded layer 48 and an N reach- through area 47 in contact with this layer 48, contact regions 46-1 and 47-1 in the P-well region 46 and the N reach-through region 47 are short-circuitted, and a common metal contact 59 is formed. A thickness W in the P-well region 46 is suppressed to a minimum, so as to allow the transistor operation of parasitic NPN transistor formed from the N region 44, P-well region 46 and N - embedded layer 48. PNPN thyristor structure is formed, so as to make this parasitic PNP transistor parallel with the PNP transistor and problems caused by increase in the collector resistance of P-well region are canceled.

    ECL CIRCUIT
    4.
    发明专利
    ECL CIRCUIT 失效

    公开(公告)号：JPH03147422A

    公开(公告)日：1991-06-24

    申请号：JP26324790

    申请日：1990-10-02

    Applicant: IBM

    Inventor： PIEERU MORIE ,  JIYANNPOORU NIYUTSUTSU ,  PASUKARU TANOFU

    IPC: H03K19/013 ,  H03K19/086

    Abstract: PURPOSE: To obtain optimal DC/AC connection to a self-reference front end amplifier for supplying a complementary output signal to a true push-pull output buffer stage by including a biasing/ combining means connected to one of power supplies in a circuit family. CONSTITUTION: The base of a transistor(TR) TDN which supplies a pulldown current necessary for high-speed falling is driven by a signal S via the biasing/ combining block BB included in a front end amplifier 31. In DC, the block BB maintains the potential of nodes M and B in an appropriate value according to the level of logic data applied to a circuit input. The node M is biased so as to define the appropriate voltage threshold value and noise resistance of the front end amplifier 31. Then, in AC, the block BB ensures high-speed signal transmission from node M to node B. The base emitter capacitance CBE of a diode connecting Tr TC is useful to accelerate the conducting of the Tr TDN.

    COMPLEMENTARY EMITTER FOLLOWER DRIVER
    7.
    发明专利
    COMPLEMENTARY EMITTER FOLLOWER DRIVER 失效

    公开(公告)号：JPH02268016A

    公开(公告)日：1990-11-01

    申请号：JP5288890

    申请日：1990-03-06

    Applicant: IBM

    Inventor： JIERAARU BUDON ,  PIEERU MORIE ,  SEIKI OGURA ,  DOMINIIKU OME ,  PASUKARU TANOFU ,  FURANKU WARAARU

    IPC: H03K19/086 ,  H03F1/30 ,  H03F3/30 ,  H03K17/56 ,  H03K17/567 ,  H03K17/66 ,  H03K19/01 ,  H03K19/013 ,  H03K19/018 ,  H03K19/08

    Abstract: PURPOSE: To quicken the operating speed and to reduce current consumption by providing a voltage converter circuit between NPN and PNP output transistors(TRs), selecting a DC voltage shift to be a shift to warrant both a minimum crossover current and a minimum delay and setting the shift point to be an operating point. CONSTITUTION: Two output bipolar TRs, an upper NPNT 1 and a lower PNPT 2 are connected by a common coupling node N and a 1st power supply voltage VH and a 2nd power supply voltage GND are given to both ends of the TRs T1, T2. The output node N is connected to a terminal 15, at which an output signal VOUT is available and a voltage conversion circuit SA1 is placed between a base and a node of each TR. Then the base node is driven by a logic signal IN 1 fed from a preceding drive circuit and the complementary emitter follower driver is operated at a conduction limit independently of a threshold level of the TRs.

Patent Agency Ranking