公开(公告)号：US3542550A

公开(公告)日：1970-11-24

申请号：US3542550D

申请日：1966-09-30

Applicant: IBM

Inventor： CONRAD ERNEST E ,  ESCH RONALD P ,  HALLEN ROBERT L ,  LEONARD RICHARD A ,  PLISKIN WILLIAM A

IPC: H01L21/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/485 ,  G03C5/00 ,  H05K3/28

CPC classification number: H01L23/3157 ,  H01L21/00 ,  H01L23/291 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/95 ,  H01L2924/00

公开(公告)号：US3497407A

公开(公告)日：1970-02-24

申请号：US3497407D

申请日：1966-12-28

Applicant: IBM

Inventor： ESCH RONALD P ,  PLISKIN WILLIAM A

IPC: C23F1/10 ,  C23F1/14 ,  H01L21/308 ,  H01L21/311 ,  H01L23/29 ,  H01L23/485 ,  H01L7/00

CPC classification number: H01L23/291 ,  H01L21/31111 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/173 ,  H01L2924/00

公开(公告)号：FR2316745A1

公开(公告)日：1977-01-28

申请号：FR7615571

申请日：1976-05-17

Applicant: IBM

Inventor： ESCH RONALD P

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L21/82

公开(公告)号：CA1049157A

公开(公告)日：1979-02-20

申请号：CA254958

申请日：1976-06-16

Applicant: IBM

Inventor： ESCH RONALD P

IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/78 ,  H01L29/04 ,  H01L29/34

Abstract: FET DEVICE WITH REDUCED OVERLAP CAPACITANCE AND METHOD OF MANUFACTURE A metal gate transistor is fabricated to have reduced gate overlap of source/drain regions and increased oxide thickness over the diffused regions whereby parasitic capacitance is reduced and switching speed is increased. The method comprises the steps of (1) selecting an appropriate insulating thickness over a semiconductor substrate, (2) forming source/drain diffused regions in the substrate through openings in the insulating layer at appropriate diffusion temperatures, (3) selecting an appropriate drivein and regrowth temperature whereby the insulating layer thickness over the diffused region is greater than that over the non-diffused region and out diffusion of the diffused regions is minimized, (4) etching the region between the source/drain to form a gate area and (5) growing a prescribed gate insulation thickness for a metal gate whereby the gate insulation overlap of the diffused region and the thickness of the gate insulation overlap of the diffused region reduce the parasitic capacitance and increase the switching speed of the resulting metal gate transistor relative to prior art transistors.

公开(公告)号：CA859683A

公开(公告)日：1970-12-29

申请号：CA859683D

Applicant: IBM

Inventor： ESCH RONALD P ,  PLISKIN WILLIAM A