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    Method for detecting exposure of a base material through an overlying coating
    2.
    发明授权
    Method for detecting exposure of a base material through an overlying coating 失效
    通过过度涂层检测基体材料的接触的方法

    公开(公告)号：US3580066A

    公开(公告)日：1971-05-25

    申请号：US3580066D

    申请日：1969-06-19

    Applicant: IBM

    Inventor： PLISKIN WILLIAM A ,  TAYLOR JAMES E

    IPC: H01L21/66 ,  C23F1/00 ,  H01L21/306 ,  H01L23/29 ,  G01N13/00

    CPC classification number: H01L23/291 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The method for determining the completeness of etching of an oxide from a silicon semiconductor device discloses that bare silicon surfaces are hydrophobic while clean freshly etched oxide surfaces are hydrophilic. To determine whether the silicon is exposed, and therefore free of any oxide film subsequent to etching, the device is cooled and subjected to a stream of moist gas and observed under a microscope. If the etching process by which small holes are formed is incomplete, oxide will remain in the hole and therefore a film of condensed water will form in the holes indicating incomplete etching. If the etching process has been properly completed in the holes, bare silicon will remain causing the moisture to form in small droplets. The form of the moisture can be observed through the microscope.

    9.
    发明专利
    未知

    公开(公告)号：FR2333349A1

    公开(公告)日：1977-06-24

    申请号：FR7629973

    申请日：1976-09-30

    Applicant: IBM

    Inventor： ABOAF JOSEPH A ,  BROADIE ROBERT W ,  PLISKIN WILLIAM A

    IPC: H01L21/76 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/331 ,  H01L21/762 ,  H01L29/73

    Abstract: A semiconductor device, such as a transistor, integrated circuit or the like, having a pattern of oxidized and densified porous silicon regions extending onto one of its major surfaces for isolating regions of the semiconductor is manufacturable by a relatively simple process. The process involves forming porous silicon regions in the surface of the semiconductor body such as a silicon wafer, in the areas where dielectric isolation between semiconductor devices is desired. The porous silicon regions are then oxidized at a temperature sufficient to completely oxidize the porous silicon. The oxidiation is such that the oxidized porous silicon extends above the surface of the semiconductor wafer. The oxidized porous silicon regions are then subjected to a temperature higher than the oxidizing temperature utilized in the previous step to cause the densification of the oxidized porous silicon regions. The result of this densification step is the collapse of the porous oxide to a dense structure which is substantially planar with the surface of the semiconductor wafer. This densified silicon dioxide structure has an etch rate which is substantially the same as thermally grown silicon dioxide.

    METHOD FOR FORMING A PLANARIZED INTEGRATED CIRCUIT
    10.
    发明专利
    METHOD FOR FORMING A PLANARIZED INTEGRATED CIRCUIT 未知

    公开(公告)号：CA1166763A

    公开(公告)日：1984-05-01

    申请号：CA404055

    申请日：1982-05-28

    Applicant: IBM

    Inventor： PLISKIN WILLIAM A ,  RISEMAN JACOB

    IPC: H01L21/31 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L21/76 ,  H01L27/00

    Abstract: FI 9-81-045 METHOD FOR FORMING A PLANARIZED INTEGRATED CIRCUIT A method is given for forming a planarized integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy has been formed on the principal surface of the product. A glass layer is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that silicon and has a softening temperature of less than about 1200.degree.C. The thermal coefficient of expansion approximates that of silicon to reduce stress problems in the integrated circuit structure. The relatively low softening temperature is required for the next step of heating the structure to cause the flow of glass on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass down to the device elements of the integrated circuit. The interconnection metallurgy is formed over the surface of the glass and through the openings of the glass to interconnect the device elements of the integrated circuit. The glass may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods.

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