Process for controlling insulating film thickness across a semiconductor wafer
    1.
    发明授权
    Process for controlling insulating film thickness across a semiconductor wafer 失效
    用于控制半导体晶片上的绝缘膜厚度的工艺

    公开(公告)号:US3899372A

    公开(公告)日:1975-08-12

    申请号:US41151873

    申请日:1973-10-31

    Applicant: IBM

    Abstract: The invention is a process of fabricating semiconductor devices including an insulating film across the surface that has a planar configuration. Alternatively, the film may be of uniform thickness and non-planar configuration. Both the planar and uniform thickness characteristics of the insulating film permit openings to be formed therein without over etching a defined surface area and conductors to be formed thereon without broadening. An important feature of the invention is utilizing the differential growth rate of films on semiconductor surfaces and/or selection of a suitable initial film thickness as a diffusion mask. The initial film thickness also contributes to a planar or uniform film thickness or other configuration across the device.

    Abstract translation: 本发明是制造半导体器件的方法,该半导体器件包括跨过表面的绝缘膜,该绝缘膜具有平面构型。 或者,膜可以具有均匀的厚度和非平面构造。 绝缘膜的平面和均匀厚度特性都允许在其中形成开口,而不会过度蚀刻限定的表面积,并且在其上形成的导体不会变宽。 本发明的一个重要特征是利用半导体表面上的膜的差分生长速率和/或适当的初始膜厚度的选择作为扩散掩模。 初始膜厚度还有助于平面或均匀的膜厚度或跨装置的其它构型。

    HIGHLY INTEGRATED MEMORY MATRIX AND METHOD FOR ITS PRODUCTION

    公开(公告)号:DE2862271D1

    公开(公告)日:1983-07-07

    申请号:DE2862271

    申请日:1978-10-23

    Applicant: IBM

    Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

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