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    Integrated optically coupled light emitter and sensor
    1.
    发明授权
    Integrated optically coupled light emitter and sensor 失效
    集成光耦合光发射器和传感器

    公开(公告)号：US3881113A

    公开(公告)日：1975-04-29

    申请号：US42847173

    申请日：1973-12-26

    Applicant: IBM

    Inventor： RIDEOUT VINCENT LEO ,  WOODALL JERRY MACPHERSON

    IPC: H01L33/00 ,  H01L27/15 ,  H01L31/173 ,  G02F1/28 ,  H01L15/00

    CPC classification number: H01L31/173

    Abstract: An optically coupled light emitting diode and photo detector is disclosed, which includes an isolation region made from the same semiconductor material as the light emitting diode and photo detector. The structure involved consists basically of four semiconductor regions, one pair of which is separated from another pair by a semiconductor isolation region. The isolation region is of the same semiconductor material as the pairs of semiconductor regions which form a light emitting diode and a photo detector. By using an isolation region of the same semiconductor material as that of the light emitting diode and the photo diode, an integrated device is provided which eliminates index of refraction and lattice constant mismatches between the light emitter and optical detector. The integrated device is fabricated from a single semiconductor material gallium aluminum arsenide and is fabricated using well known liquid phase or other epitaxial growth techniques. The resulting structure is completely symmetrical and has the unusual feature that it can be operated bidirectionally, i.e., the light emitting and photo detecting functions are completely interchangeable.

    Abstract translation: 公开了一种光耦合的发光二极管和光电检测器，其包括由与发光二极管和光电检测器相同的半导体材料制成的隔离区域。 所涉及的结构基本上由四个半导体区域组成，其中一对通过半导体隔离区域与另一对分离。 隔离区域与形成发光二极管和光电检测器的成对半导体区域具有相同的半导体材料。 通过使用与发光二极管和光电二极管相同的半导体材料的隔离区域，提供了消除光发射器和光学检测器之间的折射率和晶格常数不匹配的集成器件。 集成器件由单个半导体材料镓砷化铝制成，并且使用公知的液相或其它外延生长技术制造。 所得到的结构是完全对称的，并且具有可以双向操作的不寻常的特征，即发光和光检测功能是完全可互换的。

    2.
    发明专利
    未知

    公开(公告)号：DE2527969A1

    公开(公告)日：1976-01-08

    申请号：DE2527969

    申请日：1975-06-24

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO ,  WALKER EDWARD JOHN

    IPC: H01L27/088 ,  H01L21/00 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L21/311 ,  H01L21/316 ,  H01L21/32 ,  H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/73 ,  H01L29/78 ,  H01L21/18

    Abstract: Densely packed integrated circuit arrays for high speed memory and logic applications are fabricated using silicon semiconductor field-effect transistors (FET) which are electrically isolated one from the other by fully recessed oxide isolation regions. The method of fabrication is featured by the reduction of detrimental source to drain conduction along the side-wall of the recessed oxide to a level less than that of the main channel of the FET. Ion implantation is used to provide additional doping concentrations in the silicon substrate adjacent to the sidewall region and underneath the recessed oxide. The excess dopant underneath the recessed oxide serves as a parasitic-channel stopper. Sidewall doping is facilitated by implanting into canted sidewalls in the silicon substrate prior to the formation of the recessed oxide therein. The canted side-walls are achieved by utilizing an anisotropic etch in combination with a oriented p-conductivity type substrate.

    HIGHLY INTEGRATED MEMORY MATRIX AND METHOD FOR ITS PRODUCTION
    4.
    发明专利
    HIGHLY INTEGRATED MEMORY MATRIX AND METHOD FOR ITS PRODUCTION 未知

    公开(公告)号：DE2862271D1

    公开(公告)日：1983-07-07

    申请号：DE2862271

    申请日：1978-10-23

    Applicant: IBM

    Inventor： ESCH RONALD PHILIP ,  FOLSOM ROBERT MARTIN ,  CHANG-YIH LIU ,  RIDEOUT VINCENT LEO ,  SODERMAN DONALD ARVID ,  WENNING GEORGE THOMAS

    IPC: G11C11/401 ,  G11C5/06 ,  G11C11/404 ,  G11C11/4097 ,  H01L21/033 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/08 ,  H01L21/72 ,  G11C11/24 ,  G11C11/34

    Abstract: A dynamic random access memory is fabricated on a monolithic chip of semiconductor material. The memory is formed of an array of memory cells controlled for reading and writing by word and bit lines which are selectively connected to the cells. Each cell is a single field effect transistor structure having improved electrical charge storage capability. The improved charge storage capability of each cell is provided by an electrical capacitance structure uniquely arranged and formed as an integral portion of the field effect transistor structure. The gate electrode of each field effect transistor structure is connected to a predetermined one of said word lines. The drain of each field effect transistor is connected to a predetermined one of said bit lines. The source of each field effect transistor structure is integrally connected to and forms a portion of the uniquely arranged electrical capacitance structure of the field effect transistor structure. The electrical capacitance or storage node structure of each cell has increased electrical charge storage capacity and may be considered as a single capacitor. The single (storage) capacitor of each cell is provided between the source of the field effect transistor, a source of reference potential (reference plane) and the monolithic semiconductor substrate on which the memory is fabricated. The arrangement of the memory cells, the structure and material of each of the memory cells, and a method of fabricating the entire memory is disclosed. Also disclosed is an improved field effect transistor structure and process for fabricating same. The process of fabrication, cell arrangement and the improved storage node of each memory cell, as structurally fabricated and uniquely arranged, provides a monolithic memory having improved density and operating characteristics.

    METHOD OF PRODUCING FIELD-EFFECT TRANSISTORS OF THE MOS TYPE WITH SELF-ALIGNED GATE AND CONTACT VIAS
    5.
    发明专利
    METHOD OF PRODUCING FIELD-EFFECT TRANSISTORS OF THE MOS TYPE WITH SELF-ALIGNED GATE AND CONTACT VIAS 未知

    公开(公告)号：DE2967441D1

    公开(公告)日：1985-05-30

    申请号：DE2967441

    申请日：1979-06-11

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/32 ,  H01L21/336 ,  H01L21/762 ,  H01L21/31 ,  H01L21/76

    Abstract: A fabrication method is disclosed for providing self-aligned (i.e., misregistration tolerant or "borderless") contact vias for electrical connections between metal interconnection lines and underlying doping semiconductive regions of an integrated circuit. The described method utilizes an oxidation barrier layer material which is patterned twice to provide, first, the recessed oxide isolation regions and, later, the self-aligned contact vias. An example of an n-channel FET embodiment is described wherein self-aligned contact vias are provided between aluminum interconnection lines and n-type doped source and drain regions. In the described method, at least a portion of the normally present misregistration region or border is eliminated between the boundary of a recessed isolation oxide and the boundary of the via. The latter is ultimately coincident with the boundary of an underlying doped region. Elimination of contact borders advantageously reduces the overall area required for the contact, and consequently, reduces the overall surface area of the integrated circuit chip. Additionally, the metal step coverage at the contact edges is improved over prior art etched contact vias. The self-aligned contact via is achieved by repeated patterning of an oxidation barrier coupled with the intermediate step of thermally growing a thick insulation oxide layer over areas wherein devices such as FET's or bipolar transistors will be formed.

    9.
    发明专利
    未知

    公开(公告)号：DE2716691A1

    公开(公告)日：1977-12-01

    申请号：DE2716691

    申请日：1977-04-15

    Applicant: IBM

    Inventor： DENNARD ROBERT HEATH ,  RIDEOUT VINCENT LEO

    IPC: H01L27/10 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L27/04

    Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).

    10.
    发明专利
    未知

    公开(公告)号：DE2458745A1

    公开(公告)日：1975-07-10

    申请号：DE2458745

    申请日：1974-12-12

    Applicant: IBM

    Inventor： RIDEOUT VINCENT LEO ,  WOODALL JERRY MACPHERSON

    IPC: H01L33/00 ,  H01L27/15 ,  H01L31/173 ,  H01L31/16

    Abstract: An optically coupled light emitting diode and photo detector is disclosed, which includes an isolation region made from the same semiconductor material as the light emitting diode and photo detector. The structure involved consists basically of four semiconductor regions, one pair of which is separated from another pair by a semiconductor isolation region. The isolation region is of the same semiconductor material as the pairs of semiconductor regions which form a light emitting diode and a photo detector. By using an isolation region of the same semiconductor material as that of the light emitting diode and the photo diode, an integrated device is provided which eliminates index of refraction and lattice constant mismatches between the light emitter and optical detector. The integrated device is fabricated from a single semiconductor material gallium aluminum arsenide and is fabricated using well known liquid phase or other epitaxial growth techniques. The resulting structure is completely symmetrical and has the unusual feature that it can be operated bidirectionally, i.e., the light emitting and photo detecting functions are completely interchangeable.

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