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    Unconditionally stable, open loop operational amplifier
    1.
    发明授权
    Unconditionally stable, open loop operational amplifier 失效
    无连续稳定，开环操作放大器

    公开(公告)号：US3569848A

    公开(公告)日：1971-03-09

    申请号：US3569848D

    申请日：1968-12-12

    Applicant: IBM

    Inventor： ESTEBAN DANIEL J

    IPC: H03F1/08 ,  H03F3/30 ,  H03F3/45 ,  H03F3/18 ,  H03F3/68

    CPC classification number: H03F1/083 ,  H03F3/3091 ,  H03F3/45071

    Abstract: An open loop semiconductor operational amplifier having a differential amplifying input stage, an output stage having high input and low output impedance, and an intermediate stage interconnecting the input and output stage and having low input impedance and high output impedance. The three stages are collectively responsive to an applied input signal so as to maintain unconditional stability up to unity gain operation without external feedback circuitry.

    THREE PHASED PIPELINED SIGNAL PROCESSOR
    2.
    发明专利
    THREE PHASED PIPELINED SIGNAL PROCESSOR 未知

    公开(公告)号：CA1248638A

    公开(公告)日：1989-01-10

    申请号：CA501494

    申请日：1986-02-10

    Applicant: IBM

    Inventor： JONES GARDNER D JR ,  LARSEN LARRY D ,  ESTEBAN DANIEL J

    IPC: G06F9/48 ,  G06F9/38 ,  G06F17/10

    Abstract: THREE PHASED PIPELINED SIGNAL PROCESSOR This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.

    4.
    发明专利
    未知

    公开(公告)号：DE3687666T2

    公开(公告)日：1993-08-12

    申请号：DE3687666

    申请日：1986-03-11

    Applicant: IBM

    Inventor： LARSEN LARRY DONALD ,  ESTEBAN DANIEL J

    IPC: G06F9/38 ,  G06F17/10 ,  G06F15/31

    Abstract: The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. @Interrupt protection is therefore required for these types of branching actions as well.

    5.
    发明专利
    未知

    公开(公告)号：DE3687666D1

    公开(公告)日：1993-03-18

    申请号：DE3687666

    申请日：1986-03-11

    Applicant: IBM

    Inventor： LARSEN LARRY DONALD ,  ESTEBAN DANIEL J

    IPC: G06F9/38 ,  G06F17/10 ,  G06F15/31

    Abstract: The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. @Interrupt protection is therefore required for these types of branching actions as well.

    BRANCH CONTROL IN A THREE PHASE PIPELINED SIGNAL PROCESSOR
    10.
    发明专利
    BRANCH CONTROL IN A THREE PHASE PIPELINED SIGNAL PROCESSOR 未知

    公开(公告)号：CA1250667A

    公开(公告)日：1989-02-28

    申请号：CA501725

    申请日：1986-02-12

    Applicant: IBM

    Inventor： LARSEN LARRY D ,  ESTEBAN DANIEL J

    IPC: G06F9/38 ,  G06F17/10

    Abstract: BRANCH CONTROL IN A THREE PHASE PIEPLINED SIGNAL PROCESSOR The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.

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