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公开(公告)号：US3571712A
公开(公告)日：1971-03-23
申请号：US3571712D
申请日：1969-07-30
Applicant: IBM
Inventor： HELLWARTH GEORGE A , JONES GARDNER D JR
IPC: H04L27/156 , H04L27/233 , H04B1/16
CPC classification number: H04L27/1563 , H04L27/2331
Abstract: The digital FSK/PSK detector demodulates digital data from a frequency shift keyed modulation signal (FSK) or a phase shift keyed modulation signal (PSK) for moderate data rates including at least 1200 bits per second and is capable of operating over switching networks. The digital FSK/PSK detector comprises a binary amplitude quantizer, a clock, a digital time quantizer, a digital delay coacting with an Exclusive-OR circuit for detecting the digital data signal from the FSK/PSK modulated signal and a digital filter and smoothing circuit for eliminating undesirable noise from the digital data signal.
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公开(公告)号：US3539725A
公开(公告)日：1970-11-10
申请号：US3539725D
申请日：1968-07-12
Applicant: IBM
Inventor： HELLWARTH GEORGE A , JONES GARDNER D JR
CPC classification number: H04B3/141
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公开(公告)号：US3576575A
公开(公告)日：1971-04-27
申请号：US3576575D
申请日：1968-11-21
Applicant: IBM
Inventor： HELLWARTH GEORGE A , JONES GARDNER D JR
CPC classification number: H03M1/00 , H03M1/1066
Abstract: Apparatus for converting binary coded digital signals into analog signals, in which the initial digital signal is at first converted into a pulse whose duration is representative of said digital signal, then integrated. Also disclosed are some improvements allowing harmonics to be reduced, more particularly by combining a first pulse whose duration is representative of the binary value of the digital signal with a second pulse whose duration is representative of the binary complement of the value of said digital signal.
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公开(公告)号：US3633170A
公开(公告)日：1972-01-04
申请号：US3633170D
申请日：1970-06-09
Applicant: IBM
Inventor： JONES GARDNER D JR
CPC classification number: H04L25/03133
Abstract: In a data receiver binary-coded analog signal samples are applied to the delay element of a digital filter of the transversal-type. The samples are logically combined and weighted to provide a numeric digital output with reference to a threshold without analog reconversion.
Abstract translation: 在数据接收机中，二进制编码的模拟信号样本被应用于横向数字滤波器的延迟元件。 将样本逻辑组合并加权，以提供参考阈值的数字数字输出，无需模拟重新转换。
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公开(公告)号：CA1181876A
公开(公告)日：1985-01-29
申请号：CA417188
申请日：1982-12-07
Applicant: IBM
Inventor： ESTEBAN DANIEL J , JONES GARDNER D JR , ROGERS LEE S
IPC: H04M11/06 , H03M7/30 , H04B1/66 , H04B14/04 , H04J1/00 , H04J3/00 , H04J3/04 , H04J3/16 , H04J3/17 , H04J4/00 , H04J6/02
Abstract: The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.
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Patent Agency Ranking
公开(公告)号：CA1186077A
公开(公告)日：1985-04-23
申请号：CA415731
申请日：1982-11-17
Applicant: IBM
Inventor： JONES GARDNER D JR
Abstract: INTERLEAVED DIGITAL DATA AND VOICE COMMUNICATIONS SYSTEM APPARATUS AND METHOD The disclosed invention allows digital data to be integrated with a digital voice signal in a simple manner that does not affect the voice transmission quality. Digital data is inserted in quiet or "no speech" portions of the voice signal stream when such quiet periods are detected. No flags, headers, or other indications are necessary upon the insertion of digital data. The digital data is encoded in a two byte pattern in which the scaling bits are set high and the sign bit alternates in each eight bit byte. Four bits of each byte are thus reserved for scaling and sign purposes, but the remaining four bits are available for data transmission. Setting the three scaling bits high and alternating the sign bit has the effect of indicating to the receiver that voice is not present. This is so because the scaling bits and alternating sign bit will be decoded under the PCM coding technique to indicate an out of scale four kilohertz tone that is not allowable within the transmission path requirement of the Bell System or the CCITT in Europe. Recognition of such a signal by the receiver permits a detector to block the output at a speech terminal and to strip the scale bits from the input two byte patterns and pass the remaining bits as data to a data output.
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公开(公告)号：CA1102002A
公开(公告)日：1981-05-26
申请号：CA280454
申请日：1977-06-13
Applicant: IBM
Inventor： JONES GARDNER D JR
Abstract: A companded digital delta modulator which can encode both voice and voice band modem signals over a wide range of input levels is shown. The companding method or algorithm is based on measuring bit stream correlation and can be scaled to give substantially maximum performance over a wide range of signal tones. The algorithm has a low sensitivity to digital channel errors, thus making it suitable for signal coding for satellite channels and the like. In addition, the digital design permits common hardware to simultaneously serve a large number of lines, thus permitting the substantial savings in the hardware cost per line. A further aspect of the invention concerns the ability to handle multiple bit delta modulation as well ?s single bit delta bit modulation in the above environment.
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公开(公告)号：CA1063247A
公开(公告)日：1979-09-25
申请号：CA239234
申请日：1975-11-04
Applicant: IBM
Inventor： JONES GARDNER D JR
Abstract: DIGITAL AUTOMATIC GAIN CONTROL CIRCUIT A digital automatic gain control circuit in which the input signal is multiplied by a gain control parameter whose value is generated in a feedback loop such that the resultant product has specified constant metric.
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公开(公告)号：CA881104A
公开(公告)日：1971-09-14
申请号：CA881104D
Applicant: IBM
Inventor： HELLWARTH GEORGE A , JONES GARDNER D JR
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