公开(公告)号：DE69609430D1

公开(公告)日：2000-08-31

申请号：DE69609430

申请日：1996-02-06

Applicant: IBM

Inventor： PECHANEK GERALD G ,  VASSILIADIS STAMATIS ,  GLOSSNER CLAIR J ,  LARSEN LARRY D

IPC: G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80

Abstract: A plurality of processor elements (PEs) are connected in a cluster by a common instruction bus to an instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is broadcast from the instruction memory over the instruction bus to each PE in the cluster. The instruction includes an opcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on an operand from one of the operand registers in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.

公开(公告)号：CA1103356A

公开(公告)日：1981-06-16

申请号：CA278019

申请日：1977-05-10

Applicant: IBM

Inventor： LARSEN LARRY D

IPC: H03M5/00 ,  G06K7/10 ,  G11B20/10 ,  G11B20/14 ,  H03M5/12 ,  H03M5/14 ,  H04L25/48 ,  H04L25/49 ,  H03K9/08 ,  H03K13/01

Abstract: A METHOD OF DECODING WAVEFORMS A method for reading or decoding the self clocking encoded data content of digital data bits encoded in the standard F2F or in phase shift format is described. The method is useful for decoding F2F or phase shift code signals presented in the form of optic, magnetic, or electric signal variations presented to a decoding apparatus for the extraction of data therefrom. The technique utilizes the measurement of the interval of time or distance elapsing between two like polarity signal transitions to determine the data content of that segment of the waveform bounded by the two similar polarity transitions. The data content of that portion of the waveform or signal stream is defined in accordance with a logical matrix of values corresponding to the F2F or phase shift code formats used.

公开(公告)号：FR2353999A1

公开(公告)日：1977-12-30

申请号：FR7713445

申请日：1977-04-26

Applicant: IBM

Inventor： LARSEN LARRY D

IPC: H03M5/00 ,  G06K7/10 ,  G11B20/10 ,  G11B20/14 ,  H03M5/12 ,  H03M5/14 ,  H04L25/48 ,  H04L25/49 ,  H03K13/24

Abstract: A method for reading or decoding the self clocking encoded data content of digital data bits encoded in the standard F2F or in phase shift format is described. The method is useful for decoding F2F or phase shift code signals presented in the form of optic, magnetic, or electric signal variations presented to a decoding apparatus for the extraction of data therefrom. The technique utilizes the measurement of the interval of time or distance elapsing between two like polarity signal transitions to determine the data content of that segment of the waveform bounded by the two similar polarity transitions. The data content of that portion of the waveform or signal stream is defined in accordance with a logical matrix of values corresponding to the F2F or phase shift code formats used.

公开(公告)号：CA1248638A

公开(公告)日：1989-01-10

申请号：CA501494

申请日：1986-02-10

Applicant: IBM

Inventor： JONES GARDNER D JR ,  LARSEN LARRY D ,  ESTEBAN DANIEL J

IPC: G06F9/48 ,  G06F9/38 ,  G06F17/10

Abstract: THREE PHASED PIPELINED SIGNAL PROCESSOR This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.

公开(公告)号：CA1250667A

公开(公告)日：1989-02-28

申请号：CA501725

申请日：1986-02-12

Applicant: IBM

Inventor： LARSEN LARRY D ,  ESTEBAN DANIEL J

IPC: G06F9/38 ,  G06F17/10

Abstract: BRANCH CONTROL IN A THREE PHASE PIEPLINED SIGNAL PROCESSOR The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.

公开(公告)号：CA1000382A

公开(公告)日：1976-11-23

申请号：CA178372

申请日：1973-08-08

Applicant: IBM

Inventor： HAAS LEE C ,  LARSEN LARRY D ,  WEST LYNN P

IPC: H04L12/403

Abstract: A polling scheme is disclosed in which a plurality of remote terminals or stations sharing a single communication channel are polled by a central station at a high speed to solicit responses therefrom. The central station can effectively handle responses from only one remote station at a time and, since a plurality of stations are polled, the possibility of contention between more than one remote station trying to respond during the same time period exists. If contention does occur, a second poll of possible contenders is conducted at a slow rate of speed to resolve the contention.