EXTENDED ERROR CORRECTION FOR PACKAGE ERROR CORRECTION CODES

    公开(公告)号:CA1231456A

    公开(公告)日:1988-01-12

    申请号:CA488364

    申请日:1985-08-08

    Applicant: IBM

    Abstract: EXTENDED ERROR CORRECTION FOR PACKAGE ERROR CORRECTION CODES An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.

    3.
    发明专利
    未知

    公开(公告)号:DE3684788D1

    公开(公告)日:1992-05-21

    申请号:DE3684788

    申请日:1986-01-02

    Applicant: IBM

    Abstract: An extended error correction code operation particularly applicable to a code that can correct any number of errors in one sub-field or package but can only detect the existence of any number of errors in two sub-fields of a code word. If the initial pass of the data through the error correction code (ECC) logic (12) indicates an uncorrected error, the data is complemented and restored in the memory (10) and then reread. The retrieved data is recomplemented and again passed through the ECC logic (12). If an uncorrected error persists, then a bit-by-bit comparison (34) is performed between the originally read data (32) and the retrieved complemented data (30) to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed (20, 36, 38) and then the changed data word is passed through the ECC logic. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code logic can correct the remaining errors in the remaining sub-fields.

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