公开(公告)号：CA1231456A

公开(公告)日：1988-01-12

申请号：CA488364

申请日：1985-08-08

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  CHEN CHIN-LONG ,  EVANS EDWARD K

IPC: G06F11/10 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00 ,  H03M13/03 ,  H03M13/19 ,  G06F11/00

Abstract: EXTENDED ERROR CORRECTION FOR PACKAGE ERROR CORRECTION CODES An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.

公开(公告)号：DE3684788D1

公开(公告)日：1992-05-21

申请号：DE3684788

申请日：1986-01-02

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  CHEN CHIN-LONG ,  EVANS EDWARD K

IPC: G06F11/10 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/42 ,  H03M13/00 ,  H03M13/03 ,  H03M13/19

Abstract: An extended error correction code operation particularly applicable to a code that can correct any number of errors in one sub-field or package but can only detect the existence of any number of errors in two sub-fields of a code word. If the initial pass of the data through the error correction code (ECC) logic (12) indicates an uncorrected error, the data is complemented and restored in the memory (10) and then reread. The retrieved data is recomplemented and again passed through the ECC logic (12). If an uncorrected error persists, then a bit-by-bit comparison (34) is performed between the originally read data (32) and the retrieved complemented data (30) to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed (20, 36, 38) and then the changed data word is passed through the ECC logic. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code logic can correct the remaining errors in the remaining sub-fields.

公开(公告)号：DE68923828D1

公开(公告)日：1995-09-21

申请号：DE68923828

申请日：1989-05-17

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  COLE JACQUELINE MORRIS ,  HAZELZET BRUCE G ,  KROLAK DAVID J ,  LI HEHCHING HARRY ,  OZA BHARAT J ,  WEAVER A FRANK

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/06 ,  G06F13/16

Abstract: A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide semiconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.

公开(公告)号：DE68923828T2

公开(公告)日：1996-03-28

申请号：DE68923828

申请日：1989-05-17

Applicant: IBM

Inventor： ARLINGTON DAVID L ,  COLE JACQUELINE MORRIS ,  HAZELZET BRUCE G ,  KROLAK DAVID J ,  LI HEHCHING HARRY ,  OZA BHARAT J ,  WEAVER A FRANK

IPC: G06F12/16 ,  G06F11/10 ,  G06F12/06 ,  G06F13/16

Abstract: A "smart" memory card architecture and interface provides significantly increased performance, in part, by using fast access dynamic random access memory (DRAM) technologies which allows up to 8-byte data transfers from the memory card every 27ns after the initial access. The 27ns transfer rate includes the time required for error correction code (ECC), parity generation, and other reliability functions. Only two complementary metal oxide semiconductor (CMOS) integrated circuit (IC) logic chips or modules provide all the function required. The simplicity and flexibility afforded by the "smart" memory card approach provides a means to allow one card interface to be used with a broad range of hardware technologies and in different systems. The architecture of the memory card provides a full range of direct and partial store operations in a manner transparent to the system.