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公开(公告)号：FR2409574A1
公开(公告)日：1979-06-15
申请号：FR7822192
申请日：1978-07-21
Applicant: IBM
Inventor： FARIS SADEG M
Abstract: A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell. Diverson of the enabling current is, in turn, achieved by the switching of a serially disposed Josephson device which switches in response to the presence of two half-select currents in that device. Any othersimilarly serially disposed device in an unselected memory cell encounters only a single half-select current and, under such circumstances, cannot switch to control its associated storage gate. Any other unselected cell encounters, at most, a single half-select current.
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公开(公告)号：FR2396458A1
公开(公告)日：1979-01-26
申请号：FR7805796
申请日：1978-02-23
Applicant: IBM
Inventor： FARIS SADEG M
IPC: H01L39/22 , H03K5/1532 , H03K3/38 , H03K17/92
Abstract: A self-resetting Josephson device circuit is disclosed which responds to one transition of a circuit input by producing a short output pulse, and which resets itself in response to another, complementary transition of said circuit input. The Josephson device circuit includes a first and second Josephson device, one coupling a dc source to a current sink, said second connected in series with an inductor between said current source and sink. The circuit input, which is of a square waveform, is applied, in series, to first control circuits of the first and second Josephson devices. The second Josephson device has a second control circuit to which dc is applied of polarity opposite to the current in the first control circuit and of an amplitude substantially the same as the amplitude in the first control circuit when said circuit input is present. An output circuit includes a third Josephson device coupled in series with a second inductor and a resistor, with the series circuit coupled to said dc source. With the output circuit including the third Josephson device connected across the first Josephson device, an output pulse is produced across the second inductance and resistance on a high going transition of the circuit input. On the other hand, if the output circuit is connected across the second Josephson device then an output taken across the second inductor and resistance is produced in response to a low going transition of the circuit input. In either case, the circuit responds to the complementary transition by resetting itself.
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公开(公告)号：CA1098216A
公开(公告)日：1981-03-24
申请号：CA298267
申请日：1978-03-06
Applicant: IBM
Inventor： FARIS SADEG M
IPC: H03M7/02 , G11C11/44 , H03M7/00 , H03K19/195 , H03K3/38
Abstract: LOOP DECODER FOR JOSEPHSON MEMORY ARRAYS Decoder circuit arrangements for use with Josephson memory device arrays are disclosed. In one circuit of N stages, an input circuit consists of a Josephson junction and a shunting impedance connected across the junction by means of a matched transmission line. The transmission line has two output portions each of which controls the actuation or nonactuation of a pair of devices of circuits similar to the above-described circuit which are disposed in series in a pair of branches of a serially disposed superconducting loop of a first stage. Each branch has a serially disposed address gate to which true and complement address signals are applied. Each succeeding stage is similar to the first stage except that each branch of each succeeding stage contains twice as many circuits similar to the above-mentioned first stage circuit. Each stage provides a pair of output portions from each circuit in each branch and these outputs are connected so that the outputs of one circuit are connected to an actuable device in each branch of a succeeding stage. YO9-76-067 -1-
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公开(公告)号：FR2435165A1
公开(公告)日：1980-03-28
申请号：FR7905100
申请日：1979-02-20
Applicant: IBM
Inventor： FARIS SADEG M
IPC: G11C11/44 , H01L39/22 , H03K3/38 , H03K17/92 , H03K19/195
Abstract: A polarity switch which utilizes Josephson interferometers and low drive currents is disclosed. Single ended and double ended polarity switches which are electrically the same include a pair of circuits interconnected so that the application of a pair of signals to the circuits applies a current of one polarity or the other to a utilization circuit connected to the pair of circuits. Each of the pair of circuits includes a Josephson device which carries gate current; a current path shunting the device having a transformer secondary disposed serially in the path and another Josephson device serially disposed in the same current path. The transformer secondary is coupled to a primary through which a current is passed at the outset of the memory cycle. A current is induced in the current path of one of the pair of circuits which is in opposition to the gate current flowing in the Josephson device carrying that current. The induced current and the gate current effectively cancel one another resulting in a total current of zero flowing in the Josephson device. Then, a decoder output control line which is disposed in electromagnetically coupled relationship with both of the Josephson devices of the other of the pair of circuit switches them to the voltage state causing current to be diverted into an interconnection line which is connected to the utilization circuit.
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公开(公告)号：CA1158725A
公开(公告)日：1983-12-13
申请号：CA360335
申请日：1980-09-16
Applicant: IBM
Inventor： FARIS SADEG M
Abstract: ULTRA HIGH RESOLUTION JOSEPHSON SAMPLING TECHNIQUE. A circuit is provided for sampling and accurately reproducing unknown signals with picosecond resolution, which could be electrical, optical, x-ray, gamma ray, or a particle signal. The circuit comprises a super-conductive monitor gate having at least two states which are distinguishable from one another. The monitor gate could be, for example, comprised of a Josephson device or a superconducting quantum interference device (SQUID). Switching means, including a source of the unknown signal, are provided to switch the state of the monitor gate. This switching means includes a sampling pulse source and a bias current source which are combined with the unknown signal to change the state of the monitor gate. A noise elimination means is also provided including a lock-in amplifier, a comparator, and a feedback loop. A time averaging technique eliminates any incorrect indications resulting from noise. A timing means establishes a timing reference and sampling delay, and includes the sampling pulse source, delay lines, and a trigger pulse source connected to the source of the unknown signal and to the sampling pulse source. A display, such as an x-y recorder or oscilloscope, indicates the unknown signal. The circuit has applications in all devices where fast unknown waveform must be measured exactly, and in the field of non-equilibrium and superconductivity, where exceptionally high resolution and sensitivity are required. YO9-79-076
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Patent Agency Ranking
公开(公告)号：CA1100194A
公开(公告)日：1981-04-28
申请号：CA298268
申请日：1978-03-06
Applicant: IBM
Inventor： FARIS SADEG M
IPC: H03K5/1532 , H01L39/22 , H03K3/38 , H03K17/92 , H03K5/153
Abstract: SELF-RESETTING JOSEPHSON DEVICE CIRCUIT A self-resetting Josephson device circuit is disclosed which responds to one transition of a circuit input by producing a short output pulse, and which resets itself in response to another, complementary transition of said circuit input. The Josephson device circuit includes a first and second Josephson device, one coupling a dc source to a current sink, said second connected in series with an inductor between said current source and sink. The circuit input, which is of a square waveform, is applied, in series, to first control circuits of the first and second Josephson devices. The second Josephson device has a second control circuit to which dc is applied of polarity opposite to the current in the first control circuit and of an amplitude substantially the same as the amplitude in the first control circuit when said circuit input is present. An output circuit includes a third Josephson device coupled in series with a second inductor and a resistor, with the series circuit coupled to said dc source. With the output circuit including the third Josephson device connected across the first Josephson device, an output pulse is produced across the second inductance and resistance on a high going transition of the circuit input. On the other hand, if the output circuit is connected across the second Josephson device then an output taken across the second inductor and resistance is produced in response to a low going transition of the circuit input. In either case, the circuit responds to the complementary transition by resetting itself.
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公开(公告)号：DE2811188A1
公开(公告)日：1979-05-17
申请号：DE2811188
申请日：1978-03-15
Applicant: IBM
Inventor： FARIS SADEG M
IPC: H03K5/1532 , H01L39/22 , H03K3/38 , H03K17/92
Abstract: A self-resetting Josephson device circuit is disclosed which responds to one transition of a circuit input by producing a short output pulse, and which resets itself in response to another, complementary transition of said circuit input. The Josephson device circuit includes a first and second Josephson device, one coupling a dc source to a current sink, said second connected in series with an inductor between said current source and sink. The circuit input, which is of a square waveform, is applied, in series, to first control circuits of the first and second Josephson devices. The second Josephson device has a second control circuit to which dc is applied of polarity opposite to the current in the first control circuit and of an amplitude substantially the same as the amplitude in the first control circuit when said circuit input is present. An output circuit includes a third Josephson device coupled in series with a second inductor and a resistor, with the series circuit coupled to said dc source. With the output circuit including the third Josephson device connected across the first Josephson device, an output pulse is produced across the second inductance and resistance on a high going transition of the circuit input. On the other hand, if the output circuit is connected across the second Josephson device then an output taken across the second inductor and resistance is produced in response to a low going transition of the circuit input. In either case, the circuit responds to the complementary transition by resetting itself.
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公开(公告)号：CA1194610A
公开(公告)日：1985-10-01
申请号：CA435248
申请日：1983-08-24
Applicant: IBM
Inventor： FARIS SADEG M , MOSKOWITZ PAUL A , DAVIDSON ARTHUR , SAI-HALASZ GEORGE A
Abstract: ROOM TEMPERATURE CRYOGENIC TEST INTERFACE This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station, with the cryogenic chip attached, extends into the liquid helium reservoir. The second chip station is in the room temperature environment required for semiconductor operation. Proper semiconductor operating temperature is achieved by a heater wire and control thermocouple in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus.
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公开(公告)号：CA1109561A
公开(公告)日：1981-09-22
申请号：CA305412
申请日：1978-06-14
Applicant: IBM
Inventor： FARIS SADEG M
IPC: G11C11/44
Abstract: SUPERCONDUCTING MEMORY ARRAY CONFIGURATIONS WHICH AVOID SPURIOUS HALF-SELECT CONDITION IN UNSELECTED CELLS OF THE ARRAY A number of memory array configurations which avoid a spurious half-select condition in unselected cells of a superconducting memory array is disclosed. The memory arrays incorporate memory cells which include at least single Josephson junction disposed in a superconducting loop wherein binary information is stored in the form of at least one circulating current. For example, no circulating current can represent a binary zero, while a single circulating current can represent a binary one. In another instance, counter-rotating circulating currents can represent a binary one and a binary zero. The circulating current in combination with a half-select current, during writing of a selected memory cell, may, because of poor margins in adjacent memory cells, spuriously write information into an unselected memory cell when the half-select current is applied simultaneously to a number of memory cells which includes a selected memory cell. By providing means for applying a control magnetic field to only the selected memory cell, spurious writing of an unselected memory cell is avoided. This is accomplished in a number of embodiments by causing the application of the half-select current (which normally provides the control magnetic field to a memory cell) to divert a previously applied half-select or enabling current to the memory cell into another path so that the previously applied half-select or enabling current now acts as a control current for switching the storage gate of the selected memory cell. Diversion of the enabling current is, in turn, achieved by the switching of a serially disposed Josephson device which switches in response to the presence of two half-select currents in that device. Any other similarly serially disposed device in an unselected memory cell encounters only a single half-select current and, under such circumstances, cannot switch to control its associated storage gate. Any other unselected cell encounters, at most, a single half-select current. In another arrangement, the initially applied half-select current enables a plurality of gates to which a second half select current can be applied. When the second-half select current is applied, only that enabled gate associated with the line to which the second half-select current is applied switches, diverting the second half-select current into another path which controls the storage device of only the selected cell.
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公开(公告)号：DE2909222A1
公开(公告)日：1980-01-03
申请号：DE2909222
申请日：1979-03-09
Applicant: IBM
Inventor： FARIS SADEG M
IPC: G11C11/44 , H01L39/22 , H03K3/38 , H03K17/92 , H03K19/195
Abstract: A polarity switch which utilizes Josephson interferometers and low drive currents is disclosed. Single ended and double ended polarity switches which are electrically the same include a pair of circuits interconnected so that the application of a pair of signals to the circuits applies a current of one polarity or the other to a utilization circuit connected to the pair of circuits. Each of the pair of circuits includes a Josephson device which carries gate current; a current path shunting the device having a transformer secondary disposed serially in the path and another Josephson device serially disposed in the same current path. The transformer secondary is coupled to a primary through which a current is passed at the outset of the memory cycle. A current is induced in the current path of one of the pair of circuits which is in opposition to the gate current flowing in the Josephson device carrying that current. The induced current and the gate current effectively cancel one another resulting in a total current of zero flowing in the Josephson device. Then, a decoder output control line which is disposed in electromagnetically coupled relationship with both of the Josephson devices of the other of the pair of circuit switches them to the voltage state causing current to be diverted into an interconnection line which is connected to the utilization circuit.
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