公开(公告)号：CA1163729A

公开(公告)日：1984-03-13

申请号：CA386686

申请日：1981-09-25

Applicant: IBM

Inventor： FANG FRANK F ,  SAI-HALASZ GEORGE A

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L29/772 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

Abstract: YO980019 A field effect transistor having operating characteristics based on the control and modulation of the punchthrough phenomenon as well as the space charge limited conduction of channel current. The channel region between the source and the drain regions is appropriately doped p-type such that the n+ doped source and drain depletion regions overlap. The overlapped region is such that in the absence of the gate field it has a potential barrier high enough to prevent injection of electrons for channel conduction, and low enough to be modulated to below the kT/q barrier height criterion by the gate- and the source-to-drain fields. The actual barrier height potential is determined by the doping and channel length. When a positive voltage is applied to the gate, the gate field will cause the potential in the channel to be reduced much the same way as the external field affects an insulator. In addition to the gate field, the sourcedrain potential introduces a longitudinal field which also modulates and distorts the barrier. Alternate structures have insulating substrate or semiconductor substrate and buried layer forming the barrier.

公开(公告)号：FR2394142A1

公开(公告)日：1979-01-05

申请号：FR7803452

申请日：1978-02-01

Applicant: IBM

Inventor： CHANG LEROY L ,  ESAKI LEO ,  SAI-HALASZ GEORGE A

IPC: G11C19/28 ,  G11C11/34 ,  G11C11/35 ,  G11C13/06 ,  H01L21/203 ,  H01L21/8247 ,  H01L29/15 ,  H01L29/788 ,  H01L29/792 ,  H01L29/861

公开(公告)号：CA1189981A

公开(公告)日：1985-07-02

申请号：CA430329

申请日：1983-06-14

Applicant: IBM

Inventor： FANG FRANK F ,  SAI-HALASZ GEORGE A

IPC: H01L29/76

Abstract: PUNCH THROUGH MODULATED SEMICONDUCTOR DEVICE A field effect transistor having operating characteristics based on the control and modulation of the punch through phenomenon. The channel region between the source and the drain regions is appropriately doped such that the source and drain depletion regions overlap when no potential is applied between source and drain. The overlapped region in the absence of a gate field has a potential barrier. A gate voltage modulates the barrier to below the kT/q parameter. The source-to-drain fields also modulate the barrier.

公开(公告)号：CA1194610A

公开(公告)日：1985-10-01

申请号：CA435248

申请日：1983-08-24

Applicant: IBM

Inventor： FARIS SADEG M ,  MOSKOWITZ PAUL A ,  DAVIDSON ARTHUR ,  SAI-HALASZ GEORGE A

IPC: H01L39/24 ,  F17C13/00 ,  G01R13/34 ,  G01R31/28 ,  G01R31/26

Abstract: ROOM TEMPERATURE CRYOGENIC TEST INTERFACE This interface permits the testing of high speed semiconductor devices (room-temperature chips) by a Josephson junction sampling device (cryogenic chip) without intolerable loss of resolution. The interface comprises a quartz pass-through plug which includes a planar transmission line interconnecting a first chip station, where the cryogenic chip is mounted, and a second chip station, where the semiconductor chip to be tested is temporarily mounted. The pass-through plug has a cemented long half-cylindrical portion and short half-cylindrical portion. The long portion carries the planar transmission line, the ends of which form the first and second chip mounting stations. The short portion completes the cylinder with the long portion for part of its length, where a seal can be achieved, but does not extend over the chip mounting stations. Sealing is by epoxy cement. The pass-through plug is sealed in place in a flange mounted to the chamber wall. The first chip station, with the cryogenic chip attached, extends into the liquid helium reservoir. The second chip station is in the room temperature environment required for semiconductor operation. Proper semiconductor operating temperature is achieved by a heater wire and control thermocouple in the vicinity of each other and the second chip mounting station. Thermal isolation is maintained by vacuum and seals. Connections for power and control, for test result signals, for temperature control and heating, and for vacuum complete the test apparatus.