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    METHOD FOR CONNECTING SURFACES OF TWO COPPERS OR COPPER ALLOYS
    2.
    发明专利
    METHOD FOR CONNECTING SURFACES OF TWO COPPERS OR COPPER ALLOYS 失效

    公开(公告)号：JPH10256733A

    公开(公告)日：1998-09-25

    申请号：JP3947798

    申请日：1998-02-23

    Applicant: IBM

    Inventor： FARQUHAR DONALD SETON

    IPC: H05K3/36 ,  B23K20/02 ,  B23K20/233 ,  H05K1/11 ,  H05K3/32 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

    Abstract: PROBLEM TO BE SOLVED: To realize strong connecting of copper to copper, without the use of temperature of a melting point or higher for copper by microetching at least one copper or copper alloy surface to bring it into contact, and laminating it at specific temperature and pressure. SOLUTION: Two boards are microetched in an aqueous solution of sodium peroxide at about 20 deg.C. Two circuit boards aligned before connecting have a dielectric board 1 using polytetrafluoroethylene as a base material, an embedded circuit line 2, an inner circuit line 3, an external circuit line 4, and a plated through-hole 5. The two surfaces are brought into contact with one another, and laminated at least at about 300 degrees to less than the melting point of copper at least at a pressure of about 105.45 kgf/cm . Thus, superior connecting force is exhibited, and numerous steps necessary for conventional connecting method can be omitted.

    METHOD OF INJECTION MOLDED FLIP CHIP ENCAPSULATION
    3.
    发明专利
    METHOD OF INJECTION MOLDED FLIP CHIP ENCAPSULATION 未知

    公开(公告)号：MY132903A

    公开(公告)日：2007-10-31

    申请号：MYPI9802315

    申请日：1998-05-25

    Applicant: IBM

    Inventor： FARQUHAR DONALD SETON ,  PAPATHOMAS KONSTANTINOS

    IPC: H01L23/28 ,  H01L21/56 ,  H01L21/60

    Abstract: THE ELECTRICAL INTERCONNECTIONS BETWEEN AN INTEGRATED CIRCUIT CHIP ASSEMBLY ARE ENCAPSULATED AND REINFORCED WITH A HIGH VISCOSITY ENCAPSULANT MATERIAL IN A SINGLE STEP MOLDING PROCESS WHEREIN A MOLD IS PLACED OVER AN INTEGRATED CIRCUIT CHIP ASSEMBLY AND ENCAPSULANT MATERIAL IS DISPENSED THROUGH AN OPENING IN THE MOLD AND FORCED AROUND AND UNDER THE INTEGRATED CIRCUIT CHIP BY EXTERNAL PRESSURE ENCAPSULATING THE INTEGRATED CIRCUIT CHIP ASSEMBLY. AN INTEGRATED CIRCUIT CHIP ASSEMBLY HAVING A REINFORCED ELECTRICAL CONNECTION WHICH IS MORE RESISTANT TO WEAKENING AS A RESULT IS STRESS CREATED BY DIFFERENCES IN COEFFICIENT OF THERMAL EXPANSION BETWEEN THE INTEGRATED CIRCUIT CHIP AND THE SUBSTRATE TO WHICH THE INTEGRATED CIRCUIT IS ATTACHED IS PRODUCED.

    METHOD OF AND APPARATUS FOR INTRODUCING INTO AMOULDED HOUSING A SPHERICAL CONTACT BEARING STRUCTURE
    5.
    发明专利
    METHOD OF AND APPARATUS FOR INTRODUCING INTO AMOULDED HOUSING A SPHERICAL CONTACT BEARING STRUCTURE 未知

    公开(公告)号：PL337511A1

    公开(公告)日：2000-08-28

    申请号：PL33751198

    申请日：1998-06-12

    Applicant: IBM

    Inventor： FARQUHAR DONALD SETON ,  PAPATHOMAS KONSTANTINOS

    IPC: H01L21/56 ,  H01L21/60 ,  H01L23/31

    Abstract: The electrical interconnections between an integrated circuit chip assembly are encapsulated and reinforced with a high viscosity encapsulant material in a single step molding process wherein a mold is placed over an integrated circuit chip assembly and encapsulant material is dispensed through an opening in the mold and forced around and under the integrated circuit chip by external pressure encapsulating the integrated circuit chip assembly. An integrated circuit chip assembly having a reinforced electrical connection which is more resistant to weakening as a result is stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

    10.
    发明专利
    未知

    公开(公告)号：ID20490A

    公开(公告)日：1998-12-31

    申请号：ID980590

    申请日：1998-04-20

    Applicant: IBM

    Inventor： FARQUHAR DONALD SETON ,  PAPATHOMAS KONSTANTINOS

    IPC: H01L21/56 ,  G06K7/00

    Abstract: The electrical interconnections between an integrated circuit chip assembly are encapsulated and reinforced with a high viscosity encapsulant material in a single step molding process wherein a mold is placed over an integrated circuit chip assembly and encapsulant material is dispensed through an opening in the mold and forced around and under the integrated circuit chip by external pressure encapsulating the integrated circuit chip assembly. An integrated circuit chip assembly having a reinforced electrical connection which is more resistant to weakening as a result is stress created by differences in coefficient of thermal expansion between the integrated circuit chip and the substrate to which the integrated circuit chip is attached is produced.

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