公开(公告)号：EP1573553A4

公开(公告)日：2007-11-21

申请号：EP02795913

申请日：2002-12-17

Applicant: IBM

Inventor： BLANCO RAFAEL ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F12/08

CPC classification number: G06F12/0886 ,  G06F12/0864

Abstract: The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory (14). The selected line width is used in communicating with one or more processors (12, 26). This provides increased flexibility and efficiency for communicating with the memory. In particular, a register (42) can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block (38) in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache (30, 130), multiple ways (40) of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task (13, 28), a processor, and/or a performance evaluation.

Abstract translation: 本发明提供了选择性地改变存储器的线宽，即为存储器（14）选择多个线宽中的一个。 选定的线宽用于与一个或多个处理器（12,26）通信。 这为与内存进行通信提供了更高的灵活性和效率。 具体地说，寄存器（42）可以基于期望的线宽设置，并且随后在将数据定位在存储器中时使用。 选定的行宽可以与存储器中的每个数据块（38）相关联以允许同时使用多个行宽度。 当在高速缓存（30,130）中实现时，可以将高速缓存的多个路（40）作为一组处理，以在单个存储器操作期间提供数据。 线宽可以根据任务（13,28），处理器和/或性能评估而变化。

公开(公告)号：EP1673867A4

公开(公告)日：2007-07-18

申请号：EP04795023

申请日：2004-10-13

Applicant: IBM

Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: H03K19/173 ,  G06F15/78 ,  H03K19/177

CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

公开(公告)号：JP2006023859A

公开(公告)日：2006-01-26

申请号：JP2004199833

申请日：2004-07-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F17/50 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for designing an integrated circuit having latches.
SOLUTION: The logic design of logic elements and latches is prepared and the logic elements and the latches are positioned within the integrated circuit according to the logic design in order to create a physical design. During the process of creating the physical design, the latches that do not transition into the same clock cycle, the latches unrelated to the same logic function, the latches within the same clock domain, and the latches in a given physical proximity to each other are combined in order to delete any redundant latches. This process of deleting the redundant latches includes replacing at least two of the latches by a single latch. The physical design is corrected through the process of deleting the redundant latches and a test is conducted on the corrected physical design to determine whether the corrected physical design will operate as expected.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于设计具有闩锁的集成电路的方法。 解决方案：根据逻辑设计准备逻辑元件和锁存器的逻辑设计，逻辑元件和锁存器位于集成电路内，以创建物理设计。 在创建物理设计的过程中，不转换到相同时钟周期的锁存器，与相同逻辑功能无关的锁存器，同一时钟域内的锁存器和彼此给定的物理接近的锁存器是 组合以删除任何冗余锁存器。 删除冗余锁存器的这个过程包括通过单个锁存器替换至少两个锁存器。 通过删除冗余锁存器的过程来校正物理设计，并对修正的物理设计进行测试，以确定校正的物理设计是否按预期运行。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001312327A

公开(公告)日：2001-11-09

申请号：JP2001070355

申请日：2001-03-13

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: PROBLEM TO BE SOLVED: To provide a data processing system having a synchronizing interface, a partitioning clock and an I/O logic controller structure. SOLUTION: This system is provided with plural processing components 22 and each of processing components (22) is provided with plural I/O logic controllers (24). Further, this system is provided with plural clock supply sources (30) for supplying clock signals and plural multiplexers (36) connected to the plural clock supply sources and at least two of I/O logic controllers. Concerning the clock signals, frequencies or skews, namely, time delays are mutually different. Under the suitable control of a clock selection register connected to the plural multiplexers, one of plural clock signals from the clock supply sources can be supplied to at least two I/O logic controllers connected to the prescribed multiplexers.

公开(公告)号：WO2005038592A2

公开(公告)日：2005-04-28

申请号：PCT/US2004033803

申请日：2004-10-13

Applicant: IBM ,  GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

Inventor： GOODNOW KENNETH J ,  OGILVIE CLARENCE R ,  REYNOLDS CHRISTOPHER B ,  SMITH JACK R ,  VENTRONE SEBASTIAN T

IPC: G06F15/78 ,  H03K19/177 ,  G06F

CPC classification number: H03K19/17752 ,  G06F15/7867 ,  H03K19/17756 ,  H03K19/1776

Abstract: A reconfigurable logic array (RLA) system (104) that includes an RLA (108) and a programmer (112) for reprogramming the RLA on a cyclical basis. A function (F) requiring a larger amount of logic than contained in the RLA is partitioned into multiple functional blocks (FB1, FB2, FB3). The programmer contains software (144) that partitions the RLA into a function region FR located between two storage regions SR1, SR2. The programmer then programs functional region sequentially with the functional blocks of the function so that the functional blocks process in alternating directions between the storage regions. While the programmer is reconfiguring function region with the next functional block and reconfiguring one of the storage regions for receiving the output of the next functional block, data being passed from the current functional block to the next functional block is held in the other storage region.

Abstract translation: 包括RLA（108）和用于在循环基础上重编程RLA的编程器（112）的可重配置逻辑阵列（RLA）系统（104）。 需要比RLA中包含的逻辑量​​更大的函数（F）被分割成多个功能块（FB1，FB2，FB3）。 编程器包含将RLA分割成位于两个存储区域SR1，SR2之间的功能区域FR的软件（144）。 程序员然后用函数的功能块顺序地编程功能区，使得功能块在存储区之间交替方向上处理。 当编程人员用下一个功能块重新配置功能区域并重新配置用于接收下一个功能块的输出的存储区域时，从当前功能块传送到下一个功能块的数据被保存在另一个存储区域中。

公开(公告)号：AU2002360640A1

公开(公告)日：2004-07-29

申请号：AU2002360640

申请日：2002-12-17

Applicant: IBM

Inventor： VENTRONE SEBASTIAN T ,  BLANCO RAFAEL ,  SMITH JACK R

IPC: G06F12/08 ,  G06F12/0864 ,  G06F12/0886

公开(公告)号：DE10110567B4

公开(公告)日：2004-07-15

申请号：DE10110567

申请日：2001-03-06

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a plurality of I/O logic controllers (24). In addition, the system includes a plurality of clock sources (30) for providing clock signals and a plurality of multiplexers (36) connected to said plurality of clock sources and to at least two of said I/O logic controllers. The clock signals differ from one another in frequency or in skew, i.e., time delay. By appropriate control of clock select registers connected to the plurality of multiplexers, one of the plurality of clock signals from the clock sources may be provided to the two or more I/O logic controllers connected to a given multiplexer. This permits different groups of I/O logic controllers to receive different clock signals in parallel. As a consequence, the signal interface for the system is partitioned into multiple group with each group controlled by a separate clock.

公开(公告)号：DE10110567A1

公开(公告)日：2001-09-27

申请号：DE10110567

申请日：2001-03-06

Applicant: IBM

Inventor： FAUCHER MARC R ,  SMITH JACK R

IPC: G06F13/42 ,  G06F1/04 ,  G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  H03K17/00

Abstract: System has synchronous signal interface in place of 'fixed' signal interface and uses a number of multiplexers each of which is connected to a number of clock sources, to two or more of control units and to one clock selection register. Each multiplexer supplies an output signal as an answer to a clock selection signal from clock selection register. Multiplexer output goes to two or more control units of one of the clock signals.