公开(公告)号：DE3367059D1

公开(公告)日：1986-11-20

申请号：DE3367059

申请日：1983-06-30

Applicant: IBM ,  IBM FRANCE

Inventor： FERRY MICHEL ,  TREHIN JACQUES LOUIS

IPC: G05F1/46 ,  H04M19/00

Abstract: A circuit for supplying direct current to a line (a, b) from a battery via two supply resistors (RA, RB). Part of the current supplied by the battery flows in a secondary path including a resistor (R4) and a transistor (16), and is maintained at a constant value. A symmetrical and differential resistance bridge connected between the supply resistors and the line detects the transverse alternating current flowing into the battery, and means (15) are provided to cause the transistor to generate a negative-feedback alternating current whose value is adjusted to cancel said transverse alternating current.

公开(公告)号：DE69109104T2

公开(公告)日：1995-10-26

申请号：DE69109104

申请日：1991-06-28

Applicant: IBM

Inventor： CATALA GILLES ,  LASMAYOUX CASIMIR ,  FERRY MICHEL ,  VACHEE PIERRE ,  PACI ANDRE ,  BRAQUET HENRI J

IPC: H01G4/26 ,  H01G4/14 ,  H01G4/35 ,  H01R13/658 ,  H01R13/66

公开(公告)号：DE69019746T2

公开(公告)日：1996-01-25

申请号：DE69019746

申请日：1990-08-29

Applicant: IBM

Inventor： FERMIER YVAN ,  FERRY MICHEL ,  JACQUART CHRISTIAN ,  VACHEE PIERRE

IPC: G06F1/30 ,  H02H3/08 ,  H02H3/087 ,  H02J13/00

Abstract: The overload protection circuit 12 comprises a resistor bridge 20 with a low impedance sensing resistor r and high impedance resistors R1 to R4 which generates voltages Va and Vb at the inputs 32 and 34 of a comparator 22. Voltage Vb depend upon the value of the load current so that the comparator provides at its output 36 a control signal for opening the switching device 24 comprising a field effect transistor when the load current exceeds a maximum value. Resistor R5 reinforces the effect of the control signal. This circuit can be used in a system which comprises a central power supply unit 8 which powers a plurality of devices such as 4. The status of the circuit 12 is reported to the system 8 though line 14 and circuit 12 comprises a control circuit 26 which is responsive to set and reset control signals on lines 14 and 18 from the unit 8 to close or open the switch 26.

公开(公告)号：DE68913967D1

公开(公告)日：1994-04-21

申请号：DE68913967

申请日：1989-07-12

Applicant: IBM

Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H03M3/02

Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.

公开(公告)号：DE68913967T2

公开(公告)日：1994-09-22

申请号：DE68913967

申请日：1989-07-12

Applicant: IBM

Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H03M3/02

Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.

公开(公告)号：DE2615863A1

公开(公告)日：1976-11-18

申请号：DE2615863

申请日：1976-04-10

Applicant: IBM

Inventor： FERRY MICHEL

IPC: H03H11/04 ,  H03H11/02 ,  H02M5/04

Abstract: An active transformer is disclosed of the type which includes two primary terminals to which is applied a voltage v1 with a current i1, and two secondary terminals supplying a voltage v2 with a current i2. The transformer is characterized in that it includes a first circuit whose input, connected to the primary terminals, generates an input current of the form i1' = jC1 omega v1 and whose output supplies a current of the form i2'' = -jN omega v1 to the secondary. The transformer also includes a second circuit whose input, connected to the secondary terminals, generates an input current of the form i2' = jC2 omega v2, and whose output supplies a current i1'' = -jN omega v2 to the primary. The terms C1, C2 and N are respectively the dual equivalents of the terms L1, L2 and M found in the relations associated with a conventional transformer. The currents flow in such a way that they satisfy the relations i1 = i1' - i1' and i2 = i2' - i2''.

公开(公告)号：DE69019746D1

公开(公告)日：1995-06-29

申请号：DE69019746

申请日：1990-08-29

Applicant: IBM

Inventor： FERMIER YVAN ,  FERRY MICHEL ,  JACQUART CHRISTIAN ,  VACHEE PIERRE

IPC: G06F1/30 ,  H02H3/08 ,  H02H3/087 ,  H02J13/00

Abstract: The overload protection circuit 12 comprises a resistor bridge 20 with a low impedance sensing resistor r and high impedance resistors R1 to R4 which generates voltages Va and Vb at the inputs 32 and 34 of a comparator 22. Voltage Vb depend upon the value of the load current so that the comparator provides at its output 36 a control signal for opening the switching device 24 comprising a field effect transistor when the load current exceeds a maximum value. Resistor R5 reinforces the effect of the control signal. This circuit can be used in a system which comprises a central power supply unit 8 which powers a plurality of devices such as 4. The status of the circuit 12 is reported to the system 8 though line 14 and circuit 12 comprises a control circuit 26 which is responsive to set and reset control signals on lines 14 and 18 from the unit 8 to close or open the switch 26.

公开(公告)号：DE69109104D1

公开(公告)日：1995-05-24

申请号：DE69109104

申请日：1991-06-28

Applicant: IBM

Inventor： CATALA GILLES ,  LASMAYOUX CASIMIR ,  FERRY MICHEL ,  VACHEE PIERRE ,  PACI ANDRE ,  BRAQUET HENRI J

IPC: H01G4/26 ,  H01G4/14 ,  H01G4/35 ,  H01R13/658 ,  H01R13/66

公开(公告)号：CA1329831C

公开(公告)日：1994-05-24

申请号：CA577546

申请日：1988-09-15

Applicant: IBM

Inventor： FERRY MICHEL ,  JACQUART CHRISTIAN

IPC: H03M1/02 ,  G06J1/00 ,  H03M1/00 ,  H04B3/23

Abstract: Conversion system for performing either an analog-to-digital A/D conversion associated with an amplification step or either a digital-to-analog D/A conversion associated with an attenuation step. The system includes means (115) for receiving a input digital word to be processed, i.e. converted into analog and then attenuated, and means (165) for receiving an input analog value to be processed, i.e. amplified for scaling purpose and then converted into digital. It also includes an digital-to-analog D/A converter (110), an attenuator (120) for attenuating the analog output of D/A converter (110), and a comparator (150) for comparing the value of the input analog value to be processed and the output of said attenuator (120). The processing of the D/A-attenuation process is performed by means of both D/A converter (110) and attenuator (120). In order to achieve the A/D-amplification process, the system further includes means (140) for generating a sequence of digital words to the D/A converter (110), and means (220) for storing among this sequence, the digital value that minimizes the difference between both input of comparator (150). This digital value is extracted as being the digital representation of the amplified analog input value. Since both A/D-amplification and D/A-attenuation processings involve the same physical components, both processing have transfer function exactly inverse of one another. The typical use of this circuit is in echo cancellation technique. Fig. 1

公开(公告)号：DE3778702D1

公开(公告)日：1992-06-04

申请号：DE3778702

申请日：1987-10-30

Applicant: IBM

Inventor： FERRY MICHEL ,  JACQUART CHRISTIAN

IPC: H03M1/02 ,  G06J1/00 ,  H03M1/00 ,  H04B3/23

Abstract: The signal converter has a digital-to-analogue converter (110) which feeds an attenuator (120) output is compared (150) with the analogue input (165) retained by a sample-and-hold circuit (160). The result of the comparison is forward (175) to the control logic which includes a successive approximation register (276) and NAND gates (221-228) between digital word storage registers (210,220). For the analogue-to-digital conversion, a sequence of digital words is generated and the digital value minimising the difference between the two inputs to the comparator (150) is extracted as being digital representation of the amplified input.