公开(公告)号：DE3276513D1

公开(公告)日：1987-07-09

申请号：DE3276513

申请日：1982-11-26

Applicant: IBM ,  IBM FRANCE

Inventor： DELAPORTE FRANCOIS-XAVIER ,  LEBESNERAIS GERARD MAXIME ,  PANTANI JEAN-PIERRE

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/02 ,  H01L27/06 ,  H01L29/8605 ,  H03K19/0175 ,  H01L29/86

Abstract: A monolithically integrated resistive attenuator is autobiased from an input bipolar signal the amplitude of which is higher than the integrated circuit voltage supplies. The resistive attenuator is arranged in a first pocket formed in an epitaxial layer, and is connected between the input bipolar signal and ground. An intermediate tap produces an output signal. A diode and capacitor are formed in a second pocket. The diode is connected between the input bipolar signals and the epitaxial layer while the capacitor is connected between the epitaxial layer and the isolation walls thereof. The positive half-periods of the input bipolar signal charges the capacitor, which in turn biases the epitaxial layers. The attenuator, therefore, can be monolithically integrated into a silicon chip and remain isolated for all values of the input bipolar signal. The output signal produced by the attenuator is less than the integrated circuit voltage supplies so that the circuits driven by the output signal can be integrated without difficulties.

公开(公告)号：DE3371023D1

公开(公告)日：1987-05-21

申请号：DE3371023

申请日：1983-06-30

Applicant: IBM ,  IBM FRANCE

Inventor： FROMENT JEAN-CLAUDE ,  PANTANI JEAN-PIERRE ,  VERHAEGHE MICHEL

IPC: H04L29/10 ,  H03K5/02 ,  H04L5/14 ,  H04M11/06

Abstract: A monolithic module acting as the interface between a modem and leased ("LL") or switched ("SL") telephone lines, mainly characterized in that: 1. It can be formed on a silicon chip (due to the absence of electromechanical relays or similar switching means), and 2. Its architecture is such that it makes it possible, by interconnecting or "stacking" identical modules, not only to attach additional telephone lines, but also to increase the number of allowable modem configurations. The module (10, 10') comprises two controlled-type line amplifiers (DLL, DSL) which exhibit a high output impedance regardless of whether the power supplies are "on" or "off"; two controlled-type line receivers (RSL, RLL) which provide a very high input impedance whether the power supplies are "on" or "off"; and a wrap receiver (WRP) for testing the modem (to the exclusion of the telephone lines) and interconnecting or "stacking" identical modules. The figure shows an embodiment wherein two of the modules are interconnected; various configurations can be obtained depending on the logic state of the control inputs (1 to 4 for module 10 and 1' to 4' for module 10') supplied by the modem.

公开(公告)号：DE3277514D1

公开(公告)日：1987-11-26

申请号：DE3277514

申请日：1982-07-28

Applicant: IBM ,  IBM FRANCE

Inventor： CARSALADE HENRI ,  DELAPORTE FRANCOIS-XAVIER ,  PANTANI JEAN-PIERRE

IPC: H04L25/03 ,  H03K19/018 ,  H04L13/18 ,  H04L25/24 ,  H03K19/092

Abstract: An input network divides the signal arriving from a line conforming to the RS232C interface standard for application to a differential amplifier. The state of the equipment connected to the line is detected by a level detector and decision logic which responds to the output of the differential amplifier by producing a low-level signal when the input is active. The differential amplifier has two values of threshold for switching on the positive-going and negative-goinq slopes of the input voltage. Its current-mirror bias circuit may be shared by several receivers. The state indication is immunised against line noise and zero-crossing disturbances by two integrators. The circuit dissipates very little power and is realisable in monolithic integrated technology.

公开(公告)号：DE3067386D1

公开(公告)日：1984-05-10

申请号：DE3067386

申请日：1980-11-28

Applicant: IBM ,  IBM FRANCE

Inventor： DELAPORTE FRANCOIS-XAVIER ,  PANTANI JEAN-PIERRE

IPC: H01L27/04 ,  G01R31/26 ,  H01L21/66 ,  H01L21/822 ,  H01L29/94

公开(公告)号：DE68913967T2

公开(公告)日：1994-09-22

申请号：DE68913967

申请日：1989-07-12

Applicant: IBM

Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H03M3/02

Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.

公开(公告)号：DE3065192D1

公开(公告)日：1983-11-10

申请号：DE3065192

申请日：1980-10-29

Applicant: IBM

Inventor： DELAPORTE FRANCOIS XAVIER ,  LEBESNERAIS GERARD MAXIME ,  PANTANI JEAN-PIERRE

IPC: H03K5/02 ,  H03K17/082 ,  H03K19/018 ,  H03K19/00 ,  H03K17/08

Abstract: An interface circuit for exchanging digital signals between two pieces of data processing equipment is provided in integrated form in accordance with international standards, such as EIA Standards. This is achieved through modification of an operational amplifier to adapt its use to the conditions and requirements of interface circuits.

公开(公告)号：DE68913967D1

公开(公告)日：1994-04-21

申请号：DE68913967

申请日：1989-07-12

Applicant: IBM

Inventor： FERRY MICHEL ,  PANTANI JEAN-PIERRE ,  ORENGO GERARD ,  RICHTER GERARD

IPC: H03M3/02

Abstract: A sigma-delta converter including a switching component (313) controlled by a first clock (308) having determined transitions for generating a train of sigma-delta code pulses corresponding to an analog input value. The sigma-delta includes means (306, 310, 311) for generating a second clock (350) of a same frequency than the first clock and having a negative transition followed after a defined period of time (d2) by a positive transition. The determined transitions of the first clock controlling the swithing element occur during said defined period of time. There is also included means (305) controlled by the sigma-delta code pulse train and said second clock for generating a train of sigma-delta pulses being insensitive to the mismatch of the rise and fall times of said switching element (313) whereby improving the linearity and the signal-to-noise ration of the converter. The control of the said period of time allows the varying of the energy of the pulses in order to provide pulses train which, when applied to a sigma-delta decoder, provides an analog output value representative but attenuated with respect to the analog input value.